Patents by Inventor Gustav Laub, III

Gustav Laub, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit having state machine-driven flops in wrapper chains for device testing
    Patent number: 11342914
    Abstract: Integrated circuits are described that utilize internal state machine-driven logic elements (e.g., flops) within input and/or output wrapper chains that are used to test internal core logic of the integrate circuit. One or more individual logic elements of the wrapper chains within the integrated circuit is implemented as a multi-flop state machine rather than a single digital flip-flop. As multi-flop state machines, each enhanced logic element of a wrapper chain is individually configurable to output pre-selected values so as to disassociate the state machine-driven flops from signal transmission delays that may occur in the input or output wrapper chains of the integrated circuit.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 24, 2022
    Assignee: Juniper Networks, Inc.
    Inventor: Gustav Laub, III
  • INTEGRATED CIRCUIT HAVING STATE MACHINE-DRIVEN FLOPS IN WRAPPER CHAINS FOR DEVICE TESTING
    Publication number: 20210399729
    Abstract: Integrated circuits are described that utilize internal state machine-driven logic elements (e.g., flops) within input and/or output wrapper chains that are used to test internal core logic of the integrate circuit. One or more individual logic elements of the wrapper chains within the integrated circuit is implemented as a multi-flop state machine rather than a single digital flip-flop. As multi-flop state machines, each enhanced logic element of a wrapper chain is individually configurable to output pre-selected values so as to disassociate the state machine-driven flops from signal transmission delays that may occur in the input or output wrapper chains of the integrated circuit.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 23, 2021
    Inventor: Gustav Laub, III
  • Microprocessor having single poly-silicon EPROM memory for programmably controlling optional features
    Patent number: 5732207
    Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process-compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: March 24, 1998
    Assignee: Intel Corporation
    Inventors: Michael J. Allen, Gregory K. Crain, Stephen A. Fischer, Patrick P. Gelsinger, David R. Gray, Stuart T. Hopkins, Gustav Laub, III, Charles H. Lucas, Richard D. Pashley, Babak Sabi, Joseph D. Schutz, David J. Shield, Stephen F. Sullivan