Abstract: Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring.

Abstract: Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring.

Abstract: A function module using technology which allows conductive vias to be formed in a silicon substrate in order to fabricate three dimensional multifunctional processor system is described. A silicon or other semiconductor carrier having embedded active devices therein is used as a substrate for complex functional elements disposed on both sides thereof. The semiconductor substrate includes conductive vias formed therein which interconnect single chips or multichip modules disposed on either side thereof. Using drilling/plating techniques for wafer substrates electrically interconnected devices are placed on opposite sides of the substrate. Multichip modules (MCM) including the desired functions are then fabricated having input/output (I/Os) connection points which correspond to the vias formed in the substrate.

Abstract: A memory system package is provided by placing memory chips face-to-face using as an interposer a thin flexible carrier having through-carrier-connections, vias, for common memory chip I/O pads which are brought out to access external signals, either control, I/O or power. These external signals may also be wired to memory chip pads that are not common.

Abstract: A method of reducing the area of MCMs that are integral to a flexible carrier is provided. A locally complex area, i.e. multilayer MCM carrier is constructed on a flex carrier, along with other components to form a subsystem. The flex carrier provides the interface between the MCM and the system that is utilizing the function. Also, the flex carrier will receive non-complex portions of the function, e.g. low I/O devices, not required to be mounted on the complex area (MCM) of the subsystem. The locally complex functional area will contain the high performance DCA mounted components, such as custom ASICs, processors, high frequency analog parts and other high I/O chips. The MCM on flex is constructed by obtaining an appropriate flexible carrier, such as a dielectric material having electrically conductive signal lines circuitized on both sides.

Abstract: A method and apparatus is provided for allowing computer functions formed on a flexible substrate to be adjacently stacked in layered relation. Each functional island will have an electrical connector on one end thereof. The electrical connector may include a plurality of conductive pads formed over solid vias that form a surface for electrically interconnecting adjacent flexible carriers of the functional islands. The solid vias and connection pads are also used to provide electrical communication between the reference plane, signal lines and chips that make up the functional islands, and chips contained on other functional islands, or on the planar. The plural functional islands are removably affixed to the planar by reflowing joining metallurgy on the connection pads of adjacent layers, or by using a compression type connector. The remaining portions of the functional islands are then flexibly placed within the computer system with varying amounts of space between the layers.

Abstract: A method of nondestructively testing electronic chips adapted for direct attachment to metallized pads on circuitized substrate is disclosed, wherein an electrically conductive liquid eutectic joint is formed at room temperature with low pressure between electrical terminals on the chip and pads on the substrate. The eutectic joint remains liquid at test temperature, enabling test completion. At the end thereof, chips and pads are separated and any eutectic material residue thereon removed. The eutectic is preferably gallium/indium.

Abstract: A method is described for attaching circuit chips to a flexible substrate (laminate) using controlled chip collapse connection technology (C-4). The substrate is "tinned" with an alloy of eutectic composition in its contact region with the solder balls on the base of the chip. The alloy and the solder are chosen such that they are miscible. The system temperature is raised above the alloy melting point thus causing the alloy and the solder to mix, the mixture composition moving away from the eutectic composition with time and thus raising its melting point. Eventually the mixture melting point is higher than the temperature at which the system is maintained and the mixture solidifies to form a contact. In this way contact between the chip and the flexible substrate can be effected at a temperature below the melting point of the pure solder and lower than one which would result in degradation of the laminate adhesive.

Abstract: A composite substrate suitable for use as substrates for printed circuitry to which surface mountable components may be attached is disclosed. The substrate material comprises an alloy having a low coefficient of thermal expansion, to which aluminum is laminated and which is subsequently surface treated to produce a dielectric layer suitable to receive printed circuitry.