Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.

Abstract: In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum.

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.

Abstract: In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum.

Abstract: According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written to a location in storage. The location is one that is accessible to software that may be written for the machine. The state data as written is encoded. This state data may be recovered from the storage according to a decoding process. Other embodiments are also described and claimed.

Abstract: According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written to a location in storage. The location is one that is accessible to software that may be written for the machine. The state data as written is encoded. This state data may be recovered from the storage according to a decoding process. Other embodiments are also described and claimed.

Abstract: According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written to a location in storage. The location is one that is accessible to software that may be written for the machine. The state data as written is encoded. This state data may be recovered from the storage according to a decoding process. Other embodiments are also described and claimed.

Abstract: According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written to a location in storage. The location is one that is accessible to software that may be written for the machine. The state data as written is encoded. This state data may be recovered from the storage according to a decoding process. Other embodiments are also described and claimed.

Abstract: According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written to a location in storage. The location is one that is accessible to software that may be written for the machine. The state data as written is encoded. This state data may be recovered from the storage according to a decoding process. Other embodiments are also described and claimed.

Abstract: Mechanisms for improving the efficiency of bus-request scheduling are provided. In a read-write segregation mechanism the type of a selected entry in a buffer is determined. If the type of the selected entry matches the type of the last issued entry, or if there are no further entries in the buffer that match the last issued entry, the request is issued to the system bus. A temporal ordering mechanism associates a request sent to a buffer with an identifier, the identifier designating a time at which the request was originally generated. The request identifier is modified when a prior request is issued, and thereby reflects a history of prior issuances. A request is issued when the historical information recorded in the identifier indicates that the request is the earliest-issued pending request in the buffer. A third mechanism for increasing the efficiency of bus request scheduling in a buffer includes segregating lower priority cache eviction requests in a separate write-out section of the buffer.

Abstract: A method and system provides for changing processor configuration during operation of the processor system. The method and system include a control logic circuit where the control logic circuit sets a control bit to change the size of a processor array that allows disabling (defeaturing) of at least a portion of the array and enabling of a different performance operating mode for the processor system.

Abstract: A method and apparatus for predicting the outcome of a branch instruction based on the branch history of preceding branch instructions. As a sequence of instructions passes through an instruction execution pipeline, a base branch instruction is chosen, a history index is generated for the base branch instruction and subsequent branch instructions, and a transform is created for the branch instruction to be predicted. The transform is then saved. When the sequence of instructions subsequently passes through the pipeline again, the transform is retrieved and used to operate on the history index of the base branch instruction to produce a history index for the branch to be predicted. The result is used as an index into a prediction array to access the prediction logic for the branch instruction being predicted. By using the predetermined transform, a branch status prediction can be made before the branch to be predicted reaches the normal prediction stage in the pipeline.

Abstract: A method and apparatus for predicting the outcome of a branch instruction based on the branch history of preceding branch instruction. As a sequence of instructions passes through an instruction execution pipeline, a base branch instruction is chosen, a history index is generated for the base branch instruction and subsequent branch instructions, and a transform is created for the branch instruction to be predicted. When the sequence of instructions subsequently passes through the pipeline again, the transform is used to operate on the history index of the base branch instruction to produce a history index for the branch to be predicted. The result is used as an index into a prediction array to access the prediction logic for the branch instruction being predicted. By using the predetermined transform, a branch status prediction can be made before the branch to be predicted reaches the normal prediction stage in the pipeline.

Abstract: A method and system provides for changing processor configuration during operation of the processor system. The method and system include a control logic circuit where the control logic circuit sets a control bit to change the size of a processor array that allows disabling (defeaturing) of at least a portion of the array and enabling of a different performance operating mode for the processor system.

Abstract: Mechanisms for improving the efficiency of bus-request scheduling are provided. In a read-write segregation mechanism the type of a selected entry in a buffer is determined. If the type of the selected entry matches the type of the last issued entry, or if there are no further entries in the buffer that match the last issued entry, the request is issued to the system bus. A temporal ordering mechanism associates a request sent to a buffer with an identifier, the identifier designating a time at which the request was originally generated. The request identifier is modified when a prior request is issued, and thereby reflects a history of prior issuances. A request is issued when the historical information recorded in the identifier indicates that the request is the earliest-issued pending request in the buffer. A third mechanism for increasing the efficiency of bus request scheduling in a buffer includes segregating lower priority cache eviction requests in a separate write-out section of the buffer.

Abstract: An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.