Patents by Inventor Guy C. Fedorkow

Guy C. Fedorkow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8089870
    Abstract: In one example, a Cable Modem Termination System (CMTS) analyzes received service flow traffic to estimate Quality of Experience (QoE) at the endpoints. An admission control system on the CMTS uses the QoE estimate to determine whether to admit new service flows.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: January 3, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Alon S. Bernstein, Guy C. Fedorkow
  • Publication number: 20110019542
    Abstract: In one example, a Cable Modem Termination System (CMTS) analyzes received service flow traffic to estimate Quality of Experience (QoE) at the endpoints. An admission control system on the CMTS uses the QoE estimate to determine whether to admit new service flows.
    Type: Application
    Filed: July 22, 2009
    Publication date: January 27, 2011
    Applicant: Cisco Technology, Inc.
    Inventors: Alon S. Bernstein, Guy C. Fedorkow
  • Patent number: 7606158
    Abstract: Presently disclosed is an apparatus and method for returning control of bandwidth allocation and packet scheduling to the routing engine in a network communications device containing an ATM interface. Virtual circuit (VC) flow control is augmented by the addition of a second flow control feedback signal from each virtual path (VP). VP flow control is used to suspend scheduling of all VCs on a given VP when traffic has accumulated on enough VCs to keep the VP busy. A new packet segmenter is employed to segment traffic while preserving the first in, first out (FIFO) order in which packet traffic was received. Embodiments of the invention may be implemented using a two-level (per-VC and per-VP) scheduling hierarchy or may use as many levels of flow control feedback-derived scheduling as may be necessitated by multilevel scheduling hierarchies.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: October 20, 2009
    Assignee: Cisco Technology, Inc.
    Inventors: Guy C. Fedorkow, Kenneth H. Potter, Jr., Mark A. Gustlin, Christopher J. Kappler, Robert T. Olsen
  • Patent number: 7289434
    Abstract: In one embodiment, an intermediate node includes one or more active forwarding planes and one or more redundant forwarding planes. The intermediate node may also include one or more active control planes and one or more redundant control planes. A test packet is generated, in some cases by a redundant control plane, and transferred to a redundant forwarding plane. The operational state of the redundant forwarding plane is verified, at least in part, by using operational software and hardware contained in the redundant forwarding plane to forward the test packet from the redundant forwarding plane to a target line card. The target line card loops the test packet back to the redundant forwarding plane as part of the verification process. In some cases, the redundant control plane processes the looped-back test packet.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: October 30, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Guy C. Fedorkow, Gary S. Muntz, Timothy P. Donahue, Michael E. Wildt
  • Patent number: 7286532
    Abstract: An aggregation router architecture comprises a plurality of line cards coupled to at least one performance routing engine (PRE) via an interconnect system. The line cards include input cards having input ports coupled to subscribers and at least one trunk card configured to aggregate packets received from the subscriber inputs over at least one output port. The PRE performs packet forwarding and routing operations, along with quality of service functions for the packets received from each input line card over the interconnect system. The interconnect system comprises a plurality of high-speed unidirectional (i.e., point-to-point) links coupling the PRE to each line card. The point-to-point links couple the line cards to a novel logic circuit of the PRE that is configured to interface the line cards to a packet buffer and a forwarding engine of the PRE.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: October 23, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Maruthingendra P. Rachepalli, Ramesh Sivakolundu, Kenneth H. Potter, Guy C. Fedorkow, Gary S. Muntz
  • Patent number: 7230917
    Abstract: A flow bit mechanism and technique conveys per-channel flow control information pertaining to the status of output buffers located on line cards to at least one performance routing engine (PRE) of an intermediate network node, such as an aggregation router. Each line card generates a flow bit for each of its output buffers associated with an output channel. The state of the flow bit denotes a threshold reading on the depth of the output buffer, which is preferably organized as a first-in, first-out (FIFO) queue. The depth of the output queue is compared with a predetermined threshold value. If the depth of the FIFO is below the threshold, the state of the flow bit returned to the PRE indicates that more traffic can be accepted for that channel. If the depth of the FIFO is above the threshold, the state of the flow bit indicates that further traffic is denied for the channel until there is more space on the queue.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: June 12, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Guy C. Fedorkow, Gary S. Muntz
  • Patent number: 7065038
    Abstract: An apparatus and technique configures an intermediate network node, such as an aggregation router, to implement automatic protection switching (APS) redundancy among its line cards in the event of a failure to one of those cards. The APS line card redundancy provides redundancy among a pair of line cards connected to a performance routing engine of the router. Internal APS data paths are implemented in the router through the provision of an alias logic circuit that selects packet data from one of an adjacent pair of line cards and sends identical copies of data to that adjacent pair of line cards.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: June 20, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: William P. Brandt, Guy C. Fedorkow, Gary S. Muntz
  • Patent number: 7039073
    Abstract: A bound mode mechanism and technique efficiently accommodates high-bandwidth data traffic flow within an intermediate node of a computer network. The bound mode mechanism combines two half-slot line card connectors of a backplane in an aggregation router into a single full-slot line card arrangement to thereby increase the bandwidth provided to a high-speed, full-height line card of the router. The technique is also capable of accommodating generic half-slot (i.e., subslot) connectors, each of which is capable of supporting a variety of data formats. The bound mode mechanism further allows use of a high-speed trunk card without the penalty of supporting high trunk level bandwidth on all of the slot connectors of the router. The mechanism enables use of a simple backplane, while also maintaining a low pin count on a backplane logic circuit of the router.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: May 2, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: Gary S. Muntz, Guy C. Fedorkow
  • Patent number: 6769043
    Abstract: To ensure fair access to upstream trunk bandwidth among a plurality of interface units, a plurality of queues is provided in a first unit. One of the queues is associated with the first interface unit. Each of the remaining queues is associated with one of a plurality of second interface units. Local data is received by the first interface unit and forwarded to the associated queue. Data received from a second, subtended interface unit is forwarded to a queue which associated with the second interface unit. Data is then issued from the queues according to a fairness algorithm. A unique identifier is assigned to each interface unit. Associating a queue with an interface unit is done by associating the queue with the respective interface unit's identifier. In each interface unit, local data is tagged with the instant interface unit's identifier, and received data is forwarded to a queue according to the data's tag.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: July 27, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: Guy C. Fedorkow, John A. Joyce, Kent H. Hoult, Michael B. Milano, Nagarajan Swaminathan, Vijay J. Savla
  • Publication number: 20040109418
    Abstract: A technique for verifying an intermediate node that employs a forwarding plane and optionally a control plane. A test packet is generated and transferred to the forwarding plane. Using operational software and hardware, the forwarding plane forwards the test packet to a line card, which in turn “loops” the test packet back to the forwarding plane. Using operational software and hardware, the forwarding plane processes the looped-back test packet including forwarding the packet to a destination, such as a control plane, where the looped-back test packet is verified.
    Type: Application
    Filed: December 5, 2002
    Publication date: June 10, 2004
    Inventors: Guy C. Fedorkow, Gary S. Muntz, Timothy P. Donahue, Michael E. Wildt