Abstract: A method including, in a dielectric material over a contact on a substrate, forming a trench to the contact; introducing an electrode material along the sidewalls of the trench; introducing a phase change material over material along a first sidewall; and modifying the electrode material along the sidewalls such that only the material along the first sidewall acts as a conductive path between the contact and the phase change material. An apparatus including a chalcogenide memory element; a contact; and a heater element comprising two leg portions, a first leg portion coupled to the contact and the chalcogenide memory element, and only the first leg portion acts as a conductive path between the contact and the chalcogenide memory element.

Abstract: An apparatus including a contact on a substrate, a dielectric material overlying the contact, a phase change element overlying the dielectric material on a substrate, and a heater element disposed in the dielectric material and coupled to the contact and the phase change element, wherein a portion of the dielectric material comprises a thermal conductivity less than silicon dioxide. A method including introducing over a contact formed on a substrate, a dielectric material, a portion of which comprises a thermal conductivity less than silicon dioxide, introducing a heater element through the dielectric material to the contact, and introducing a phase change material over the dielectric material and the heater element.

Abstract: An apparatus including a contact on a substrate, a dielectric material overlying the contact, a phase change element overlying the dielectric material on a substrate, and a heater element disposed in the dielectric material and coupled to the contact and the phase change element, wherein a portion of the dielectric material comprises a thermal conductivity less than silicon dioxide. A method including introducing over a contact formed on a substrate, a dielectric material, a portion of which comprises a thermal conductivity less than silicon dioxide, introducing a heater element through the dielectric material to the contact, and introducing a phase change material over the dielectric material and the heater element.

Abstract: A memory system comprising memory cells and reference cells each including a programmable resistance element. The resistance state of a memory cell is determined by comparing a sense signal developed by the memory cell with a reference signal developed by one or more of the reference cells. The programmable resistance elements may comprise a phase-change material.

Abstract: A method of programming an electrically programmable phase-change memory element to the low resistance state. A first pulse of energy sufficient to transform the device from the low to high resistance states is applied, and a second pulse of energy sufficient to transform the device from the high to low resistance states is applied following the first pulse. In another programming method, the present and desired device states are compared, and programming pulses are applied only if the state of the device needs to be changed.

Abstract: An acute matrix liquid crystal display panel including 1) a plurality of liquid crystal display elements distributed in a matrix of rows and columns; 2) means for supplying video signals and display element selection signals, including row and column conductors; and 3) a plurality of paired Ovonic threshold switches and resistive elements each serially coupled between the corresponding row or column conductor and the liquid crystal display element, the Ovonic threshold switches acting as display element selection devices and current isolation devices in which the Ovonic threshold switches having an off state resistance of at least 1.times.10.sup.9 ohms.

Abstract: The present invention is a computational unit comprising a logic processing device, and a memory array deposited on top of and communicating with the logic processing device. More specifically, the present invention is a computational unit comprising a logic processing device, and electrically erasable phase change memory deposited on top of and communicating with the logic processing device.

Abstract: An active matrix liquid crystal display panel including a plurality of Ovonic threshold switches each serially coupled between the corresponding row or column conductor and the liquid crystal display element. The Ovonic threshold switches act as display element selection devices and current isolation devices. The Ovonic switches have an off-state resistance of at least 1.times.10.sup.10 ohms.

Abstract: The present invention defines a display driver for driving a flat panel display having rows and columns. The display driver has row and column drivers comprised of logic gates where each logic gate includes chalcogenide threshold switches. The logic gates of the present invention use a chalcogenide threshold switch as a means of discharging load capacitance and resetting logic gate output.

Abstract: A solid state, directly overwritable, electronic, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, multibit single cell memory or control array based upon the novel switching characteristics provided by said unique class of semiconductor materials characterized by a large dynamic range of reversible Fermi level positions. The memory or control elements from which the array is fabricated exhibit orders of magnitude higher switching speeds at remarkably reduced energy levels. The novel memory elements of the instant invention are in turn characterized, inter alia, by numerous stable and non-volatile detectable configurations of local atomic and/or electrode order, which configurations can be selectively and repeatably accessed by electric input signals of yawing energy level.

Abstract: Disclosed herein is a solid state, directly overwritable, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, single cell memory element having reduced switching current requirements and increased write/erase cycle life. The structurally modified memory element includes an electrical contact formed of amorphous silicon, either alone or in combination with a layer of amorphous carbon layer. The memory element exhibits orders of magnitude higher switching speeds at remarkably reduced switching energy levels. The novel memory elements of the instant invention are further characterized, inter alia, by at least two stable and non-volatile detectable configurations of local atomic and/or electronic order, which configurations can be selectively and repeatably accessed by electrical input signals of designated energies.

Abstract: A method for the low temperature fabrication of doped polycrystalline semiconductor alloy material. The method includes the steps of exposing a body of semiconductor alloy material to a reaction gas containing at least a source of the dopant element, and establishing an electrical potential sufficient to sputter etch the surface of said layer, while decomposing the reaction gas. This allows for the deposition of a layer of doped amorphous semiconductor alloy material upon the body of semiconductor alloy material. Thereafter, the doped layer of amorphous semiconductor alloy material is exposed to an annealing environment sufficient to at least partially crystallize said amorphous material, and activate the dopant element.

Abstract: An electrically erasable phase change memory utilizing a stoichiometrically and volumetrically balanced phase change material in which both the switching times and the switching energies required for the transitions between the amorphous and the crystalline states are substantially reduced below those attainable with prior art electrically erasable phase change memories. One embodiment of the invention comprises an integrated circuit implementation of the memory in a high bit density configuration in which manufacturing costs are correspondingly reduced and performance parameters are further improved.

Abstract: An electro-optical communication device which includes a light transmissive conduit integrally formed to interconnect a light emitter and a light detector. The length over which the light transmissive conduit extends is substantially greater than the size of either the light emitter or the light detector. In the preferred embodiment, the light emitter and the light detector are each formed from amorphous semiconductor alloy material and may be substantially surrounded by the light transmissive conduit.