Patents by Inventor Guy Caspary

Guy Caspary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12647366
    Abstract: Devices, networks, systems, methods, and processes for load balancing are described herein. A device can receive a stream of data packets. The device may generate a load balancing vector based on the stream of data packets. The device can encode the load balancing vector and can further apply substitution operation on encoded load balancing vector to generate a modified load balancing vector. The device may apply a hash function on the modified load balancing vector to generate a load balancing key. The device can determine a destination device based on the load balancing key. The device may forward the stream of data packets to the destination device. A load balancing method of the present disclosure can distribute data traffic evenly or uniformly, without traffic polarization. A load balancing system of the present disclosure can generate the load balancing key in time efficient and resource efficient manner.
    Type: Grant
    Filed: December 29, 2023
    Date of Patent: June 2, 2026
    Assignee: Cisco Technology, Inc.
    Inventors: Etgar Israeli, Elad Naor, Guy Caspary, Mel Tsai
  • Publication number: 20260016962
    Abstract: Devices, networks, systems, methods, and processes for facilitating parallel processing in ternary content addressable memory (TCAM) systems are described herein. A TCAM system including two physical TCAM blocks may detect a key-type associated with a key entry. The TCAM system can be operated in a wide search mode or a narrow search mode based on the detected key-type. In the narrow search mode, the key entry, being a narrow key, is inputted to the two physical TCAM blocks for associated data look-up. In the wide search mode, the key entry, being a wide key, is split into two segments, and one segment is inputted to one TCAM block and the other segment is inputted to the other TCAM block. The TCAM system may implement multiple logical TCAMs using the physical TCAM blocks. Thus, integrating a hybrid architecture of hardwired logic followed by programmable logic configuration, enhanced by parallel processing.
    Type: Application
    Filed: July 10, 2024
    Publication date: January 15, 2026
    Inventors: Guy Caspary, Mel Tsai
  • Publication number: 20250219945
    Abstract: Devices, networks, systems, methods, and processes for load balancing are described herein. A device can receive a stream of data packets. The device may generate a load balancing vector based on the stream of data packets. The device can encode the load balancing vector and can further apply substitution operation on encoded load balancing vector to generate a modified load balancing vector. The device may apply a hash function on the modified load balancing vector to generate a load balancing key. The device can determine a destination device based on the load balancing key. The device may forward the stream of data packets to the destination device. A load balancing method of the present disclosure can distribute data traffic evenly or uniformly, without traffic polarization. A load balancing system of the present disclosure can generate the load balancing key in time efficient and resource efficient manner.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Inventors: Etgar Israeli, Elad Naor, Guy Caspary, Mel Tsai
  • Patent number: 11695428
    Abstract: A network element is configured to efficiently load balance packets through a computer network. The network element receives a packet associated with flow attributes and generates a Load Balancing Flow Vector (LBFV) from the flow attributes. The network element partitions the LBFV into a plurality of LBFV blocks and reorders the LBFV blocks to generate a reordered LBFV. The LBFV blocks are reordered based on a reordering sequence that is different from reordering sequences on other network elements in the computer network. The network element hashes the reordered LBFV to generate a hash key for the packet and selects a next hop link based on the hash key. The next hop link connects the network elements to a next hop network element in the computer network.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: July 4, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Guy Caspary, Nadav Tsvi Chachmon, Aviran Kadosh
  • Publication number: 20220399901
    Abstract: A network element is configured to efficiently load balance packets through a computer network. The network element receives a packet associated with flow attributes and generates a Load Balancing Flow Vector (LBFV) from the flow attributes. The network element partitions the LBFV into a plurality of LBFV blocks and reorders the LBFV blocks to generate a reordered LBFV. The LBFV blocks are reordered based on a reordering sequence that is different from reordering sequences on other network elements in the computer network. The network element hashes the reordered LBFV to generate a hash key for the packet and selects a next hop link based on the hash key. The next hop link connects the network elements to a next hop network element in the computer network.
    Type: Application
    Filed: July 7, 2022
    Publication date: December 15, 2022
    Inventors: Guy Caspary, Nadav Tsvi Chachmon, Aviran Kadosh
  • Patent number: 11418214
    Abstract: A network element is configured to efficiently load balance packets through a computer network. The network element receives a packet associated with flow attributes and generates a Load Balancing Flow Vector (LBFV) from the flow attributes. The network element partitions the LBFV into a plurality of LBFV blocks and reorders the LBFV blocks to generate a reordered LBFV. The LBFV blocks are reordered based on a reordering sequence that is different from reordering sequences on other network elements in the computer network. The network element hashes the reordered LBFV to generate a hash key for the packet and selects a next hop link based on the hash key. The next hop link connects the network elements to a next hop network element in the computer network.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 16, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Guy Caspary, Nadav Tsvi Chachmon, Aviran Kadosh
  • Publication number: 20130007411
    Abstract: Disclosed are various embodiments of configurable allocation of hardware resources. In one embodiment, a processing device includes a configurable communication grid including a plurality of crossbars interconnected by intercommunication paths in a geometric configuration and a plurality of pipeline elements distributed within the configurable communication grid. Each crossbar is designed to direct communications received at an input to a selected output. Each pipeline element is communicatively coupled to an output of a first crossbar adjacent to the pipeline element and an input of a second crossbar adjacent to the pipeline element. In another embodiment, a process matrix includes a plurality of pipeline elements interconnected by a configurable communication grid. The configurable communication grid includes intercommunication paths connecting crossbars in a geometric configuration.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 3, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Michael Asa, Guy Caspary