Patents by Inventor Guy Cohen
Guy Cohen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110006367Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.Type: ApplicationFiled: September 20, 2010Publication date: January 13, 2011Applicant: International Business Machines CorporationInventors: Nicholas C.M. Fuller, Sarunya Bangsaruntip, Guy Cohen, Sebastian U. Engelmann, Lidija Sekaric, Qingyun Yang, Ying Zhang
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Patent number: 7864612Abstract: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.Type: GrantFiled: November 24, 2008Date of Patent: January 4, 2011Assignee: Spansion Israel LtdInventors: Eli Lusky, Boaz Eitan, Guy Cohen, Eduardo Maayan
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Patent number: 7816275Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.Type: GrantFiled: April 3, 2009Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Sarunya Bangsaruntip, Guy Cohen, Sebastian U. Engelmann, Lidija Sekaric, Qingyun Yang, Ying Zhang
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Publication number: 20100252810Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.Type: ApplicationFiled: April 3, 2009Publication date: October 7, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicholas C. M. Fuller, Sarunya Bangsaruntip, Guy Cohen, Sebastian U. Engelmann, Lidija Sekaric, Qingyun Yang, Ying Zhang
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Publication number: 20100255680Abstract: Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.Type: ApplicationFiled: April 3, 2009Publication date: October 7, 2010Applicant: International Business Machines CorporationInventors: Tymon Barwicz, Guy Cohen, Lidija Sekaric, Jeffrey Sleight
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Publication number: 20100193770Abstract: Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.Type: ApplicationFiled: February 4, 2009Publication date: August 5, 2010Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy Cohen, Jeffrey W. Sleight
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Patent number: 7742339Abstract: Selecting a read voltage level for a NVM cell by using an initial value for the read voltage and performing a read operation, comparing an actual number of bits found to an expected number of bits and, if there is a discrepancy between the actual number and the expected number, adjusting the read voltage level, based on variable data such as statistics available, level occupation, neighbor level, previous chunks data, and other data used during read, program or erase. For example, based on a number of missing bits, or upon a result of a previous read operation, or a result obtained at another program level, or upon how many times the memory cell has been cycled, or upon how many memory cells are at each program level, or on a number of bits at another program level in a selected chunk of memory.Type: GrantFiled: January 10, 2007Date of Patent: June 22, 2010Assignee: Saifun Semiconductors Ltd.Inventors: Arik Rizel, Guy Cohen
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Patent number: 7715237Abstract: As part of the present invention, a memory cell may be operated using reference cells having a threshold offset circuit. According to some embodiments of the present invention, a threshold offset value may be determined for a memory cell to be operated based on a location (e.g. memory segment within a memory array) of the memory cell. An input offset circuit of a global reference cell may be adjusted by the threshold offset value for the memory cell; and the memory cell may be operated (e.g. read, written or erased) using the global reference cell whose input offset circuit has been adjusted by the threshold offset value. According to some embodiments of the present invention global reference cells may consist of multiple sets of reference cells, wherein, according to some aspects, each set of the multiple sets of reference cells may be used for operating a different memory array segment.Type: GrantFiled: February 26, 2008Date of Patent: May 11, 2010Assignee: Saifun Semiconductors Ltd.Inventor: Guy Cohen
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Patent number: 7675782Abstract: The present invention is a multi-phase method, circuit and system for programming non-volatile memory (“NVM”) cells in an NVM array. The present invention may include a controller to determine when, during a first programming phase, one or more NVM cells of a first set of cells reaches or exceeds a first intermediate voltage, and to cause a charge pump circuit to apply to a terminal of the one or more cells in the first set second phase programming pulses to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.Type: GrantFiled: October 17, 2006Date of Patent: March 9, 2010Assignee: Saifun Semiconductors Ltd.Inventors: Guy Cohen, Yan Polansky
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Publication number: 20100052018Abstract: A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy can be derived from either a semiconductor nanowire or an epitaxial grown semiconductor material. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion. The lower portion of the continuous metal semiconductor alloy and the vertical pillar portion are not separated by a material interface. Instead, the two portions of the continuous metal semiconductor alloy are of unitary construction, i.e.Type: ApplicationFiled: August 26, 2008Publication date: March 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy Cohen, Christos D. Dimitrakopoulos, Alfred Grill
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Patent number: 7659200Abstract: A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.Type: GrantFiled: January 5, 2007Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Guy Cohen, Qiang Huang, Lubomyr T. Romankiw, Hariklia Deligianni
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Publication number: 20090302305Abstract: A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.Type: ApplicationFiled: August 14, 2009Publication date: December 10, 2009Applicant: International Business Machines CorporationInventors: Guy Cohen, Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw
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Publication number: 20090298292Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.Type: ApplicationFiled: August 10, 2009Publication date: December 3, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy A. Cohen, Steven A. Cordes, Sherif A. Goma, Joanna Rosner, Jeannine M. Trewhella
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Publication number: 20090231915Abstract: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.Type: ApplicationFiled: November 24, 2008Publication date: September 17, 2009Inventors: Eli Lusky, Boaz Eitan, Guy Cohen, Eduardo Maayan
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Publication number: 20090003073Abstract: Selecting a read voltage level for a NVM cell by using an initial value for the read voltage and performing a read operation, comparing an actual number of bits found to an expected number of bits and, if there is a discrepancy between the actual number and the expected number, adjusting the read voltage level, based on variable data such as statistics available, level occupation, neighbor level, previous chunks data, and other data used during read, program or erase. For example, based on a number of missing bits, or upon a result of a previous read operation, or a result obtained at another program level, or upon how many times the memory cell has been cycled, or upon how many memory cells are at each program level, or on a number of bits at another program level in a selected chunk of memory.Type: ApplicationFiled: January 10, 2007Publication date: January 1, 2009Inventors: Arik Rizel, Guy Cohen
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Patent number: 7457183Abstract: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.Type: GrantFiled: October 16, 2006Date of Patent: November 25, 2008Assignee: Saifun Semiconductors Ltd.Inventors: Eli Lusky, Boaz Eitan, Guy Cohen, Eduardo Maayan
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Publication number: 20080180999Abstract: As part of the present invention, a memory cell may be operated using reference cells having a threshold offset circuit. According to some embodiments of the present invention, a threshold offset value may be determined for a memory cell to be operated based on a location (e.g. memory segment within a memory array) of the memory cell. An input offset circuit of a global reference cell may be adjusted by the threshold offset value for the memory cell; and the memory cell may be operated (e.g. read, written or erased) using the global reference cell whose input offset circuit has been adjusted by the threshold offset value. According to some embodiments of the present invention global reference cells may consist of multiple sets of reference cells, wherein, according to some aspects, each set of the multiple sets of reference cells may be used for operating a different memory array segment.Type: ApplicationFiled: February 26, 2008Publication date: July 31, 2008Inventor: Guy Cohen
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Publication number: 20080166858Abstract: A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.Type: ApplicationFiled: January 5, 2007Publication date: July 10, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy Cohen, Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw
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Patent number: 7352627Abstract: As part of the present invention, a memory cell may be operated using reference cells having a threshold offset circuit. According to some embodiments of the present invention, a threshold offset value may be determined for a memory cell to be operated based on a location (e.g. memory segment within a memory array) of the memory cell. An input offset circuit of a global reference cell may be adjusted by the threshold offset value for the memory cell; and the memory cell may be operated (e.g. read, written or erased) using the global reference cell whose input offset circuit has been adjusted by the threshold offset value. According to some embodiments of the present invention global reference cells may consist of multiple sets of reference cells, wherein, according to some aspects, each set of the multiple sets of reference cells may be used for operating a different memory array segment.Type: GrantFiled: January 3, 2006Date of Patent: April 1, 2008Assignee: Saifon Semiconductors Ltd.Inventor: Guy Cohen
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Publication number: 20080064149Abstract: A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.Type: ApplicationFiled: October 30, 2007Publication date: March 13, 2008Applicant: International Business Machines CorporationInventor: Guy Cohen