Abstract: A digit rate reducing system for PCM signals comprises a predictor stage, an automatic gain control stage, and a quantizer stage for adaptive quantizing. The predictor stage includes a predictor and a subtractor for subtracting from a sample x.sub.n of the PCM input signal a predicted signal x.sub.pn derived from preceding samples. The subtractor provides a difference signal d.sub.n representing prediction error to the automatic gain control (AGC) stage. A divider in the AGC stage divides the difference signal d.sub.n by m, providing a divided signal e.sub.n to the quantizer stage. In this last stage, a quantizer encodes the divided signal e.sub.n into a signal Y.sub.n of reduced rate. The predictor uses a first adder which receives the predicted signal x.sub.pn and a reconstituted signal d.sub.n derived from the reduced rate signal Y.sub.n ; a plurality of shift registers and associated multipliers; and a second adder connected to the outputs of the multiplier. Shift registers T.sub.1 . . . T.sub.