Patents by Inventor Guy Drory
Guy Drory has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220342702Abstract: A heterogeneous multi-core system that executes a real-time system for an automobile includes a plurality of system-on chips in electronic communication with one another. Each system-on-chip includes a plurality of central processing units (CPUs) arranged into a plurality of logical domains. The heterogeneous multi-core system also includes a plurality of scheduled tasks that are executed based on an execution pipeline and each execute a specific set of tasks for one of the logical domains. The plurality of scheduled tasks includes at least one offset scheduled task that is executed at an offset time and a reference scheduled task located at an execution stage upstream in the execution pipeline relative to the offset scheduled task. The reference scheduled task communicates data to the offset scheduled task and the offset time represents a period of time measured relative to the reference scheduled task.Type: ApplicationFiled: April 26, 2021Publication date: October 27, 2022Inventors: Guy Drory, Gilboa Shveki
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Patent number: 10342029Abstract: A method includes detecting, using a WiFi access point, channel use data indicating traffic on a plurality of channels of an unlicensed LTE band in a wireless network. The method further includes providing the channel use data to a Long Term Evolution (LTE) access point. The method further includes selecting, using the LTE access point, a channel for use in transmitting data by the LTE access point from among the plurality of channels based on the channel use data from the WiFi access point. The method further includes providing, from the LTE access point, an indication of an upcoming transmission configured to transmit data on the channel to the WiFi access point. The method further includes broadcasting one or more messages from the WiFi access point to one or more WiFi nodes, the one or more messages configured to prevent the WiFi nodes from transmitting on the channel.Type: GrantFiled: January 9, 2018Date of Patent: July 2, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Yong Li, Guy Drory, Yonatan Cohen, Baoguo Yang, Matthew Fischer, Sharon Levy, Sindhu Verma, Shubhodeep Adhikari
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Publication number: 20180146488Abstract: A method includes detecting, using a WiFi access point, channel use data indicating traffic on a plurality of channels of an unlicensed LTE band in a wireless network. The method further includes providing the channel use data to a Long Term Evolution (LTE) access point. The method further includes selecting, using the LTE access point, a channel for use in transmitting data by the LTE access point from among the plurality of channels based on the channel use data from the WiFi access point. The method further includes providing, from the LTE access point, an indication of an upcoming transmission configured to transmit data on the channel to the WiFi access point. The method further includes broadcasting one or more messages from the WiFi access point to one or more WiFi nodes, the one or more messages configured to prevent the WiFi nodes from transmitting on the channel.Type: ApplicationFiled: January 9, 2018Publication date: May 24, 2018Inventors: Yong Li, Guy Drory, Yonatan Cohen, Baoguo Yang, Matthew Fischer, Sharon Levy, Sindhu Verma, Shubhodeep Adhikari
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Patent number: 9907085Abstract: A method includes detecting, using a WiFi access point, channel use data indicating traffic on a plurality of channels of an unlicensed LTE band in a wireless network. The method further includes providing the channel use data to a Long Term Evolution (LTE) access point. The method further includes selecting, using the LTE access point, a channel for use in transmitting data by the LTE access point from among the plurality of channels based on the channel use data from the WiFi access point. The method further includes providing, from the LTE access point, an indication of an upcoming transmission configured to transmit data on the channel to the WiFi access point. The method further includes broadcasting one or more messages from the WiFi access point to one or more WiFi nodes, the one or more messages configured to prevent the WiFi nodes from transmitting on the channel.Type: GrantFiled: September 23, 2015Date of Patent: February 27, 2018Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Yong Li, Guy Drory, Yonatan Cohen, Baoguo Yang, Matthew Fischer, Sharon Levy, Sindhu Verma, Shubhodeep Adhikari
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Patent number: 9839028Abstract: A carrier aggregation controller for providing an aggregated baseband signal from a plurality of baseband signals is provided. The controller comprises an accumulating memory, a selector and a time domain transformer. The selector is configured to add at least a first list of frequency domain samples obtained for the first baseband signal to first consecutive locations in the accumulating memory centered at a first preset location associated with the first baseband signal, and a second list of frequency domain samples obtained for the second baseband signal to second consecutive locations in the accumulating memory centered at a second preset location associated with the second baseband signal. The time domain transformer is configured to apply at least an inverse discrete Fourier transform to the frequency domain samples accumulated in the accumulating memory, obtaining the aggregated baseband signal.Type: GrantFiled: June 18, 2013Date of Patent: December 5, 2017Assignee: NXP USA, Inc.Inventors: Amit Bar-Or, Guy Drory, Gideon Kutz, Ran Zamir
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Patent number: 9572199Abstract: A multimode rake receiver comprise a common antenna interface, arranged to at least receive in a first mode a first CDMA radio channel carrying information encoded according to a first baseband modulation standard and to receive in a second mode a second CDMA radio channel carrying information encoded according to a second baseband modulation standard; and a common signal processing path, at least arranged to process in the first mode the first CDMA radio channel and in the second mode the second CDMA radio channel, wherein the common signal path comprises a common descrambling and de-spreading unit and a common hybrid code generating unit arranged to provide to the common descrambling and de-spreading unit chip codes applicable in the first mode to the first CDMA radio channel and in the second mode to the second CDMA radio channel.Type: GrantFiled: October 19, 2011Date of Patent: February 14, 2017Assignee: NXP USA, INC.Inventors: Guy Drory, Eliya Babitsky, Ron Bercovich
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Publication number: 20160143012Abstract: A carrier aggregation controller for providing an aggregated baseband signal from a plurality of baseband signals is provided. The controller comprises an accumulating memory, a selector and a time domain transformer. The selector is configured to add at least a first list of frequency domain samples obtained for the first baseband signal to first consecutive locations in the accumulating memory centered at a first preset location associated with the first baseband signal, and a second list of frequency domain samples obtained for the second baseband signal to second consecutive locations in the accumulating memory centered at a second preset location associated with the second baseband signal. The time domain transformer is configured to apply at least an inverse discrete Fourier transform to the frequency domain samples accumulated in the accumulating memory, obtaining the aggregated baseband signal.Type: ApplicationFiled: June 18, 2013Publication date: May 19, 2016Applicant: Freescale Semiconductor, Inc.Inventors: AMIT BAR-OR, GUY DRORY, GIDEON KUTZ, RAN ZAMIR
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Publication number: 20160095110Abstract: A method includes detecting, using a WiFi access point, channel use data indicating traffic on a plurality of channels of an unlicensed LTE band in a wireless network. The method further includes providing the channel use data to a Long Term Evolution (LTE) access point. The method further includes selecting, using the LTE access point, a channel for use in transmitting data by the LTE access point from among the plurality of channels based on the channel use data from the WiFi access point. The method further includes providing, from the LTE access point, an indication of an upcoming transmission configured to transmit data on the channel to the WiFi access point. The method further includes broadcasting one or more messages from the WiFi access point to one or more WiFi nodes, the one or more messages configured to prevent the WiFi nodes from transmitting on the channel.Type: ApplicationFiled: September 23, 2015Publication date: March 31, 2016Applicant: BROADCOM CORPORATIONInventors: Yong (Gordon) Li, Guy Drory, Yonatan Cohen, Baoguo Yang, Matthew Fischer, Sharon Levy, Sindhu Verma, Shubhodeep Adhikari
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Publication number: 20140220917Abstract: A multimode rake receiver comprise a common antenna interface, arranged to at least receive in a first mode a first CDMA radio channel carrying information encoded according to a first baseband modulation standard and to receive in a second mode a second CDMA radio channel carrying information encoded according to a second baseband modulation standard; and a common signal processing path, at least arranged to process in the first mode the first CDMA radio channel and in the second mode the second CDMA radio channel, wherein the common signal path comprises a common descrambling and de-spreading unit and a common hybrid code generating unit arranged to provide to the common descrambling and de-spreading unit chip codes applicable in the first mode to the first CDMA radio channel and in the second mode to the second CDMA radio channel.Type: ApplicationFiled: October 19, 2011Publication date: August 7, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Guy Drory, Eliya Babistky, Ron Bercovich
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Patent number: 8627022Abstract: A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect, coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information elemenType: GrantFiled: January 21, 2008Date of Patent: January 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Yuval Neeman, Ron Bercovich, Guy Drory, Dror Gilad, Aviel Livay, Yonatan Naor
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Patent number: 8595584Abstract: A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.Type: GrantFiled: May 19, 2008Date of Patent: November 26, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Yuval Neeman, Guy Drory, Aviel Livay, Inbar Schori
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Patent number: 8413033Abstract: A method for calculating backward state metrics of a trellis, the method includes: performing a radix-K calculation of backward state matrices of multiple states of at least one time instance of a trellis; and performing a radix-J calculation of backward state matrices of multiple states of at least one other time instance of the trellis; wherein K differs from J.Type: GrantFiled: July 24, 2009Date of Patent: April 2, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Guy Drory, Ron Bercovich, Aviel Livay, Ilia Moskovich, Yuval Neeman
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Patent number: 8200733Abstract: A method and a device having interleaving capabilities, the device comprises a first interleaver; the first interleaver comprises a first register, a second register, a first adder and a second adder; wherein the first register is coupled to the first adder and to the second adder; wherein the second register is coupled to the second adder; wherein the first adder is adapted to add a current first register value to a first coefficient to provide a next first register value that is stored at the first register; wherein the second adder is adapted to add a current first register value to a second coefficient, to a third coefficient and to a current second register value to provide an interleaved output value.Type: GrantFiled: April 15, 2008Date of Patent: June 12, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Yuval Neeman, Ron Berkovich, Guy Drory, Gilad Dror, Aviel Livay, Yonatan Naor
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Patent number: 8171384Abstract: A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration.Type: GrantFiled: June 27, 2008Date of Patent: May 1, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Guy Drory, Ron Bercovich, Yosef Kazaz, Aviel Livay, Yonatan Naor, Yuval Neeman
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Publication number: 20110060963Abstract: A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.Type: ApplicationFiled: May 19, 2008Publication date: March 10, 2011Applicant: Freescale Semiconductor, Inc.Inventors: Yuval Neeman, Guy Drory, Aviel Livay, Inbar Schori
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Publication number: 20110019781Abstract: A method for calculating backward state metrics of a trellis, the method includes: performing a radix-K calculation of backward state matrices of multiple states of at least one time instance of a trellis; and performing a radix-J calculation of backward state matrices of multiple states of at least one other time instance of the trellis; wherein K differs from J.Type: ApplicationFiled: July 24, 2009Publication date: January 27, 2011Inventors: Guy Drory, Ron Bercovich, Aviel Livay, Ilia Moskovich, Yuval Neeman
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Publication number: 20100287343Abstract: A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information elementType: ApplicationFiled: January 21, 2008Publication date: November 11, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Yuval Neeman, Ron Bercovich, Guy Drory, Dror Gilad, Aviel Livay, Yonatan Naor
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Patent number: 7760114Abstract: A method for generating an interleaved output during a decoding of a data block, the method includes: (i) selecting, in response to a row indicator, a row register and a multiplication factor to provide a selected row register and a selected multiplication factor; wherein the selected multiplication factor is responsive to a size of the data block; (ii) multiplying a value stored in the selected row register by the selected multiplication factor to provide an intermediate result; (iii) performing a modulo P operation on the intermediate result to provide a permutated result; wherein the permutated result and the value stored in the selected row register are adjacent elements of the same permutation; wherein P is responsive to a size of the data block; (iv) writing the permutated result to the selected row register; and (v) outputting a data block element that is selected in response to the permutated result.Type: GrantFiled: October 30, 2008Date of Patent: July 20, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Yuval Neeman, Guy Drory, Aviel Livay, Inbar Schori
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Publication number: 20100111291Abstract: A method for generating an interleaved output during a decoding of a data block, the method includes: (i) selecting, in response to a row indicator, a row register and a multiplication factor to provide a selected row register and a selected multiplication factor; wherein the selected multiplication factor is responsive to a size of the data block; (ii) multiplying a value stored in the selected row register by the selected multiplication factor to provide an intermediate result; (iii) performing a modulo P operation on the intermediate result to provide a permutated result; wherein the permutated result and the value stored in the selected row register are adjacent elements of the same permutation; wherein P is responsive to a size of the data block; (iv) writing the permutated result to the selected row register; and (v) outputting a data block element that is selected in response to the permutated result.Type: ApplicationFiled: October 30, 2008Publication date: May 6, 2010Inventors: Yuval NEEMAN, Guy DRORY, Aviel LIVAY, Inbar SCHORI
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Publication number: 20090327834Abstract: A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration.Type: ApplicationFiled: June 27, 2008Publication date: December 31, 2009Inventors: Guy Drory, Ron Bercovich, Yosef Kazaz, Aviel Livay, Yonatan Naor, Yuval Neeman