Abstract: A technique includes during in-service use of a memory package in a computer system, using a first interface to access a defective address memory of the memory package. The defective address memory is accessible by a manufacturer of the memory package prior to the in-service use using a second interface of the memory package other than the first interface. In connection with the in-service use of the memory package, the memory package is repair, a repair that includes storing a defective address in the defective address memory to change an address mapping for at least one cell of the storage array.

Abstract: An apparatus includes a memory module, which includes a memory array. The memory array includes rows of memory and columns of memory. The apparatus also includes at least one row of memory not in the memory array and a register. The register includes an address space and a row/column indicator. The apparatus also includes row selection logic to select the at least one row to be activated if the address from an address bus equals the register value and if the row/column indicator indicates row.

Abstract: A cache memory system utilizing asynchronous/synchronous burst counter circuitry which lessens the need for expensive, high speed data SRAM to achieve zero wait-state operation. The burst counter circuitry takes advantage of the fact that a read address is present on the address bus approximately one-halfway through the initial bus cycle (T1) during a burst read. Unlike synchronous prior art burst counters, burst counter circuitry according to the invention is configured to forward the address to asynchronous address decoders as soon as it is present, rather than waiting for the next rising edge of the processor clock. For accesses to the first cache line, the timing budget therefore includes the first complete clock cycle of a burst read (T2) plus an extra half-clock cycle from T1. The extra time is utilized to retrieve data from the data SRAM core for provision to the processor data bus at the end of the bus cycle T2.

Abstract: An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.