Abstract: A computer implemented method of detecting a fault in a system comprises the steps of executing at least three virtual machines, each virtual machine executing a same application software, in separated and isolated memory segments and in a dedicated core of a multi-core processor; the virtual machines being synchronized and concurrently executed by a common hypervisor; wherein non-faulty virtual machines provide an identical output message within a predefined time-interval; detecting a fault in an output of a virtual machine, the fault corresponding to a different output message of the faulty virtual machine. Developments include a distributed vote mechanism, pull/push mechanisms, association of output vote messages with a safety extension comprising identification information, virtual machine recovery using data context.

Abstract: A computer implemented method of detecting a fault in a system comprises the steps of executing at least three virtual machines, each virtual machine executing a same application software, in separated and isolated memory segments and in a dedicated core of a multi-core processor; the virtual machines being synchronized and concurrently executed by a common hypervisor; wherein non-faulty virtual machines provide an identical output message within a predefined time-interval; detecting a fault in an output of a virtual machine, the fault corresponding to a different output message of the faulty virtual machine. Developments include a distributed vote mechanism, pull/push mechanisms, association of output vote messages with a safety extension comprising identification information, virtual machine recovery using data context.

Abstract: A device for improving the fault tolerance of a processor installed on a motherboard, the motherboard comprising memory units and a data input/output interface, the processor being able to execute at least one application, includes: a software layer, called a hypervisor, centralizing exchanges between the said processor and the said application and implementing fault tolerance management mechanisms, and a programmable electronic component forming an interface between the processor on the one hand.