Patents by Inventor Guy Guthrie

Guy Guthrie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080098177
    Abstract: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.
    Type: Application
    Filed: December 13, 2007
    Publication date: April 24, 2008
    Inventors: Guy Guthrie, William Starke, Derek Williams, Philip Williams
  • Publication number: 20080091885
    Abstract: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.
    Type: Application
    Filed: December 13, 2007
    Publication date: April 17, 2008
    Inventors: Guy Guthrie, William Starke, Derek Williams, Philip Williams
  • Publication number: 20080077744
    Abstract: A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.
    Type: Application
    Filed: December 5, 2007
    Publication date: March 27, 2008
    Applicant: International Business Machines Corporation
    Inventors: Benjiman Goodman, Guy Guthrie, William Starke, Jeffrey Stuecheli, Derek Williams
  • Publication number: 20080077740
    Abstract: A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency.
    Type: Application
    Filed: November 29, 2007
    Publication date: March 27, 2008
    Inventors: Leo Clark, Guy Guthrie, Kirk Livingston, William Starke
  • Publication number: 20080052471
    Abstract: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 28, 2008
    Inventors: JAMES FIELDS, JR., Guy Guthrie, William Starke, Jeffrey Stuecheli
  • Publication number: 20080046651
    Abstract: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.
    Type: Application
    Filed: October 25, 2007
    Publication date: February 21, 2008
    Inventors: Leo Clark, James Fields, Guy Guthrie, Bradley McCredie, William Starke
  • Publication number: 20080040557
    Abstract: A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single update to the system memory.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 14, 2008
    Inventors: Sanjeev Ghai, Guy Guthrie, John Hollaway
  • Publication number: 20080040556
    Abstract: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 14, 2008
    Inventors: James Fields, Benjiman Goodman, Guy Guthrie, William Starke, Derek Williams
  • Publication number: 20080028155
    Abstract: In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.
    Type: Application
    Filed: August 7, 2007
    Publication date: January 31, 2008
    Inventors: JAMES FIELDS, Guy Guthrie, William Starke, Jeffrey Stuecheli
  • Publication number: 20080016284
    Abstract: According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.
    Type: Application
    Filed: September 28, 2007
    Publication date: January 17, 2008
    Inventors: BENJIMAN GOODMAN, Guy Guthrie, William Starke, Jeffrey Stuecheli, Derek Williams
  • Publication number: 20070294486
    Abstract: A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.
    Type: Application
    Filed: August 30, 2007
    Publication date: December 20, 2007
    Applicant: International Business Machines Corporation
    Inventors: Benjiman Goodman, Guy Guthrie, William Starke, Jeffrey Stuecheli, Derek Williams
  • Publication number: 20070250668
    Abstract: A data processing system includes a memory subsystem and an execution unit, coupled to the memory subsystem, which executes store instructions to determine target memory addresses of store operations to be performed by the memory subsystem. The data processing system further includes a mode field having a first setting indicating strong ordering between store operations and a second setting indicating weak ordering between store operations. Store operations accessing the memory subsystem are associated with either the first setting or the second setting. The data processing system also includes logic that, based upon settings of the mode field, inserts a synchronizing operation between a store operation associated with the first setting and a store operation associated with the second setting, such that all store operations preceding the synchronizing operation complete before store operations subsequent to the synchronizing operation.
    Type: Application
    Filed: April 25, 2006
    Publication date: October 25, 2007
    Inventors: Ravi Arimilli, Thomas Capasso, Guy Guthrie, Hugh Shen, William Starke
  • Publication number: 20070250669
    Abstract: A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for holding the target address of store operation, a data field for holding data for the store operation, and a virtual sync field indicating a presence or absence of a synchronizing operation associated with the entry. The memory subsystem further includes a store queue controller that, responsive to receipt at the memory subsystem of a sequence of operations including a synchronizing operation and a particular store operation, places a target address and data of the particular store operation within the address field and data field, respectively, of an entry in the store queue and sets the virtual sync field of the entry to represent the synchronizing operation, such that a number of store queue entries utilized is reduced.
    Type: Application
    Filed: April 25, 2006
    Publication date: October 25, 2007
    Inventors: Ravi Arimilli, Thomas Capasso, Robert Cargnoni, Guy Guthrie, Hugh Shen, William Starke
  • Publication number: 20070226427
    Abstract: A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 27, 2007
    Inventors: Guy Guthrie, William Starke, Jeffrey Stuecheli, Derek Williams
  • Publication number: 20070226426
    Abstract: A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain includes a system memory controller for a system memory and a first processing unit having a first cache memory. The second coherency domain includes a second processing unit having a second cache memory. In the first cache memory, a coherency state field associated with a storage location and an address tag is set to a first coherency state. In response to snooping an exclusive access request specifying a target address matching the address tag, the first cache memory provides a first partial response to the exclusive access request based at least in part upon the first coherency state. In response to snooping the exclusive access request, the memory controller determines whether it is responsible for the target address and provides a second partial response to the exclusive access request based at least in part upon an outcome of the determination.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 27, 2007
    Inventors: Leo Clark, James Fields, Guy Guthrie, William Starke, Derek Williams
  • Publication number: 20070226423
    Abstract: A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache memory in the first coherency domain determines a coherency state of the target memory block with respect to the cache memory. In response to the determination, the cache memory selects a scope of broadcast of an initialization request identifying the target memory block. A narrower scope including the first coherency domain and excluding the second coherency domain is selected in response to a determination of a first coherency state, and a broader scope including the first coherency domain and the second coherency domain is selected in response to a determination of a second coherency state. The cache memory then broadcasts an initialization request with the selected scope.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 27, 2007
    Inventors: Ravi Arimilli, Guy Guthrie, William Starke, Derek Williams
  • Publication number: 20070204110
    Abstract: A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping a data-invalid state update request, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and that a memory block associated with the address tag is likely cached within the first coherency domain.
    Type: Application
    Filed: February 28, 2006
    Publication date: August 30, 2007
    Inventors: Guy Guthrie, William Starke, Derek Williams
  • Publication number: 20070180196
    Abstract: A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain contains a memory controller, an associated system memory having a target memory block identified by a target address, and a domain indicator indicating whether the target memory block is cached outside the first coherency domain. During operation, the first coherency domain receives a flush operation broadcast to the first and second coherency domains, where the flush operation specifies the target address of the target memory block. The first coherency domain also receives a combined response for the flush operation representing a system-wide response to the flush operation. In response to receipt in the first coherency domain of the combined response, a determination is made if the combined response indicates that a cached copy of the target memory block may remain within the data processing system.
    Type: Application
    Filed: January 30, 2006
    Publication date: August 2, 2007
    Inventors: Guy Guthrie, John Hollaway, William Starke, Derek Williams
  • Publication number: 20070168618
    Abstract: A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.
    Type: Application
    Filed: January 17, 2006
    Publication date: July 19, 2007
    Inventors: Leo Clark, Guy Guthrie, William Starke, Jeffrey Stuecheli, Derek Williams
  • Publication number: 20070088926
    Abstract: A data processing system includes a plurality of requestors and a memory controller for a system memory. In response to receiving from the requestor a read-type request targeting a memory block in the system memory, the memory controller protects the memory block from modification, and in response to an indication that the memory controller is responsible for servicing the read-type request, the memory controller transmits the memory block to the requestor. Prior to receipt of the memory block by the requestor, the memory controller ends protection of the memory block from modification, and the requestor begins protection of the memory block from modification. In response to receipt of the memory block, the requestor ends its protection of the memory block from modification.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 19, 2007
    Inventors: James Fields, Guy Guthrie, John Hollaway, Derek Williams