Abstract: A method and apparatus for testing an integrated circuit interconnect comprises an IC having circuitry embedded in the IC capable of providing a pseudo time domain reflectometry test by launching a test transition onto the interconnect and capturing a reflection of the test transition.

Abstract: A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each programmably electrically connectable according to the hybrid binary/thermometer code in parallel between a voltage source and the signal pad. The plurality of impedance legs are partitioned into one or more set pairs of binary stepped impedance legs and corresponding thermometer stepped impedance legs. A binary set of calibration signals in the hybrid binary/thermometer code steps a given set of binary stepped impedance legs according to a binary code and a thermometer set of calibration signals in the hybrid binary/thermometer code steps the corresponding set of thermometer stepped impedance legs according to a thermometer code once per full count iteration of the binary set of calibration signals.

Abstract: A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each programmably electrically connectable according to the hybrid binary/thermometer code in parallel between a voltage source and the signal pad. The plurality of impedance legs are partitioned into one or more set pairs of binary stepped impedance legs and corresponding thermometer stepped impedance legs. A binary set of calibration signals in the hybrid binary/thermometer code steps a given set of binary stepped impedance legs according to a binary code and a thermometer set of calibration signals in the hybrid binary/thermometer code steps the corresponding set of thermometer stepped impedance legs according to a thermometer code once per full count iteration of the binary set of calibration signals.

Abstract: A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by connecting transistors with differing threshold voltages between the node and a voltage source and driving the gates of these transistors with the same driving signal.

Abstract: An electrostatic discharge (ESD) structure for use in an integrated circuit (IC). The ESD structure comprises a metallic resistor and a metallic capacitor that are electrically coupled in series to form a resistor-capacitor (RC) component having an appropriate RC time constant. The RC component maintains a level of charge between ground and a shunt node to ensure that, during an ESD event, electrostatic charge on a power supply, VDD, associated with the ESD structure is shunted via a shunt path from said power supply VDD to said ground. By using metal to create the metal resistor and capacitor, charge leakage problems that result from parasitic capacitance associated with using an RC component comprised of either a poly, active, or nwell resistor in combination a diode are eliminated. By eliminating such charge leakage problems, a more reliable RC component, and thus a more reliable RC time constant, are obtained.

Abstract: A pad driver method and apparatus is presented. The pad driver includes a dual path configuration. The dual path includes a first path and a second path. Both paths include a pre-driver. The first path and the second path communicate high voltage signals and low voltage signals. The pre-driver in the first path drives a pFET device. The pre-driver in the second path drives an nFET device. The pFET and nFET devices provide an output signal, which drives a pad. Each pre-driver further includes a first path and a second path. The first path in the pre-driver supports high voltage operation and the second path in the pre-driver supports low voltage operation.

Abstract: A system for simplifying clock construction and distribution within an integrated circuit, and for simplifying analysis within the integrated circuit. The system utilizes a memory, software stored within said memory defining functions to be performed by the system, and a processor.

Abstract: A pad driver method and apparatus is presented. The pad driver includes a dual path configuration. The dual path includes a first path and a second path. Both paths include a pre-driver. The first path and the second path communicate high voltage signals and low voltage signals. The pre-driver in the first path drives a pFET device. The pre-driver in the second path drives an nFET device. The pFET and nFET devices provide an output signal, which drives a pad. Each pre-driver further includes a first path and a second path. The first path in the pre-driver supports high voltage operation and the second path in the pre-driver supports low voltage operation.

Abstract: A method and circuit for controlling the slope of a transitioning signal on a transmission line of integrated circuit is achieved using stepwise pull-down impedance reduction/augmentation. Over a series of sequentially ordered steps, a predetermined decreasing (or increasing) impedance is connected between the transmission line and voltage source. Using certain predetermined impedance values in order, a linear slew rate on the output signal is achievable. Adjusting the time delay between each step allows the slope of the linear slew rate to be adjusted.

Abstract: A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by adjusting the source resistance of the pre-drive devices to generate a slew-controlled pre-drive signal for driving the output drive devices.

Abstract: A system for simplifying clock construction and distribution within an integrated circuit, and for simplifying analysis within the integrated circuit. The system utilizes a memory, software stored within said memory defining functions to be performed by the system, and a processor.

Abstract: A method and circuit for controlling the slope of a transitioning signal on a transmission line of integrated circuit is achieved using stepwise pulldown impedance reduction/augmentation. Over a series of sequentially ordered steps, a predetermined decreasing (or increasing) impedance is connected between the transmission line and voltage source. Using certain predetermined impedance values in order, a linear slew rate on the output signal is achievable. Adjusting the time delay between each step allows the slope of the linear slew rate to be adjusted.

Abstract: A technique for preventing high current shorts through I/O pads of an integrated circuit during power up and power down is presented. In accordance with the invention, the voltage levels of the core power supply that powers the internal circuitry of the integrated circuit and the I/O power supply that powers the input and/or output pad drivers is monitored to detect the condition wherein the core power supply is powered down and the I/O power supply is powered up. Upon detection of this condition, the pad drivers are disabled, preferably by disabling the pre-drivers that generate the pre-drive signals that drive the output driver devices. In a preferred embodiment, the process/voltage/temperature adjustment circuitry is leveraged to disable the output pads during power up and down.

Abstract: An electrostatic discharge (ESD) structure for use in an integrated circuit (IC). The ESD structure comprises a metallic resistor and a metallic capacitor that are electrically coupled in series to form a resistor-capacitor (RC) component having an appropriate RC time constant. The RC component maintains a level of charge between ground and a shunt node to ensure that, during an ESD event, electrostatic charge on a power supply, VDD, associated with the ESD structure is shunted via a shunt path from said power supply VDD to said ground. By using metal to create the metal resistor and capacitor, charge leakage problems that result from parasitic capacitance associated with using an RC component comprised of either a poly, active, or nwell resistor in combination a diode are eliminated. By eliminating such charge leakage problems, a more reliable RC component, and thus a more reliable RC time constant, are obtained.

Abstract: A latch that is insensitive to alpha particle strikes. The latch comprises input circuitry that receives an input data value to be stored in the latch, a transfer gate that is closed when the input circuitry is driving the latch to store the received data value, and a feedback circuit that drives the latch when the transfer gate is opened and the input circuitry is no longer driving the latch. When the input circuitry is driving the latch, the strength of the input circuitry is sufficient to prevent an alpha strike error from occurring in the latch. When the input circuitry is not driving the latch, the transfer gate is opened and the feedback circuit generates a feedback signal that drives the latch with sufficient strength to prevent an alpha strike error from occurring.

Abstract: A voltage reference circuit is provided, including a plurality of switching elements connected to a reference node, a voltage divider for providing a different voltage to each of the switching elements, and logic circuitry for selectively actuating the switching elements in response to a control signal provided to all of the switching elements.

Abstract: An electronic circuit and method for processing a signal, including a variable-delay transmission gate for receiving a binary input signal and propagating a delayed binary output signal corresponding to the input signal. The propagation delay in the transmission gate is controlled by two complimentary, non-binary, control signals from a current mirror that is driven by a PVT-compensated voltage follower.

Abstract: A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by adjusting the source resistance of the pre-drive devices to generate a slew-controlled pre-drive signal for driving the output drive devices.

Abstract: A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by connecting transistors with differing threshold voltages between the node and a voltage source and driving the gates of these transistors with the same driving signal.

Abstract: A binary weighted thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit. The driver circuit includes an impedance network comprising a plurality of resistive devices each programmably electrically connectable in parallel between a first voltage source and the signal pad. The resistive devices are partitioned into a plurality of sets. A first set of the resistive devices may be programmed in a binary incremental manner to electrically connect one or more of the resistive devices in the first set between the first voltage source and the signal pad. Only if all of the resistive devices in the first set are activated may a second set of the resistive devices be programmed in a binary incremental manner. Additional sets of the resistive devices may be likewise programmed only after all of the resistive devices in the previously programmed sets are activated.