Abstract: A binary signal compression device for reducing the redundant information in a sequence of binary coded signal series on the basis of lines of picture elements. This device comprises a storage stage 1 for the consecutive series, a prediction stage 2 for the even series, a substitution stage 3 which substitutes the associated error signals for the predicted signals, a coding stage 4 comprising a one-dimensional coding stage 17 for the non-predicted odd series and a coding circuit 18 for the even series, and a clock stage 5. The coding circuit 18 divides the even series in blocks of the same length and codes these blocks in accordance with the number and the position of the binary signals contained in the blocks.