Abstract: A method and system for securing CSI and DSI links using enhanced authentication and cloud tracking are disclosed. According to one embodiment, a method comprises receiving at the receiving device an encrypted information signal from the transmitting device. The encrypted information signal includes a unique identifier of the transmitting device. The method further comprises testing whether a whitelist at the receiving device includes the unique identifier of the transmitting device. The encrypted information signal is decrypted producing a retrieved information signal only if the whitelist includes the unique identifier of the transmitting device; and otherwise terminating communication with the transmitting device.

Abstract: A method and system for securing in-vehicle ethernet links are disclosed. According to one embodiment, a method comprises receiving from an authenticator, via an insecure channel, a public key of the authenticator, a random number, and a challenge. A private key of the peer that was supplied to the peer is accessed from local storage at the peer. A state machine computes a session key for the peer, based on the random number, the public key of the authenticator, and the private key of the peer. The state machine computes a peer response to the challenge using the session key for the peer and a symmetric cipher function.

Abstract: Systems and methods for generating an RTL description based on logical signal groupings are described. Logical interfaces are declared in a compressed form, and logical signal grouping is defined in a markup document. The definitions from the markup document are used by expansion scripts to populate RTL modules and encapsulate block connectivity and functionality. Multiple interfaces can be created instantly, and interface definitions for common interfaces may be easily re-defined. Default values may be assigned to module outputs for testing purposes, allowing for multi-module simulations where certain modules are shelled-out.

Abstract: An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip. A signature of these flip-flop implemented registers on the semiconductor chip is periodically captured. The signature allows for the integrity of the flip-flop implemented registers to be constantly monitored. A soft error occurring on any of the flip-flop implemented registers can be immediately detected. In response to the detection, an interrupt is raised to notify software to take action.

Abstract: A method and system for securing in-vehicle ethernet links are disclosed. According to one embodiment, a method comprises receiving from an authenticator, via an insecure channel, a public key of the authenticator, a random number, and a challenge. A private key of the peer that was supplied to the peer is accessed from local storage at the peer. A state machine computes a session key for the peer, based on the random number, the public key of the authenticator, and the private key of the peer. The state machine computes a peer response to the challenge using the session key for the peer and a symmetric cipher function.

Abstract: A method and system for securing CSI and DSI links using enhanced authentication and cloud tracking are disclosed. According to one embodiment, a method comprises receiving at the receiving device an encrypted information signal from the transmitting device. The encrypted information signal includes a unique identifier of the transmitting device. The method further comprises testing whether a whitelist at the receiving device includes the unique identifier of the transmitting device. The encrypted information signal is decrypted producing a retrieved information signal only if the whitelist includes the unique identifier of the transmitting device; and otherwise terminating communication with the transmitting device.

Abstract: An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a Benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse network, wherein the Benes routing network retrieves the packet data from the memory banks coupled to input of the Benes routing network and route the packet data to the port groups coupled to output of the Benes routing network. The on-chip crossbar further comprises a plurality of stage routing control units each associated with one of the forward routing stages and configured to generate and provide a plurality of node control signals to control routing of the packet data through the forward routing stages to avoid contention between the packet data retrieved from different memory banks at the same time.

Abstract: An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a Benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse network, wherein the Benes routing network retrieves the packet data from the memory banks coupled to input of the Benes routing network and route the packet data to the port groups coupled to output of the Benes routing network. The on-chip crossbar further comprises a plurality of stage routing control units each associated with one of the forward routing stages and configured to generate and provide a plurality of node control signals to control routing of the packet data through the forward routing stages to avoid contention between the packet data retrieved from different memory banks at the same time.

Abstract: A new approach is proposed that contemplates systems and methods to support automatic timing adjustment of a plurality of paths carrying metadata of incoming data packets in a network switch to meet their respective timing constraints. First, the paths for transmitting different pieces of metadata of incoming packets are identified in the network switch. Once the metadata paths are identified, the proposed approach identifies the timing constraints that the metadata paths need to satisfy in order for the network switch to function properly. The proposed approach then calculates the current delays of the metadata paths and determines optimal timing values of each of the metadata paths in order to meet the timing constraints. The optimal timing values of the metadata paths are then compared to the current delays of the metadata paths to identify the paths which current delay values need to be adjusted.

Abstract: Systems and methods for generating an RTL description based on logical signal groupings are described. Logical interfaces are declared in a compressed form, and logical signal grouping is defined in a markup document. The definitions from the markup document are used by expansion scripts to populate RTL modules and encapsulate block connectivity and functionality. Multiple interfaces can be created instantly, and interface definitions for common interfaces may be easily re-defined. Default values may be assigned to module outputs for testing purposes, allowing for multi-module simulations where certain modules are shelled-out.

Abstract: A new approach is proposed that contemplates systems and methods to support automatic timing adjustment of a plurality of paths carrying metadata of incoming data packets in a network switch to meet their respective timing constraints. First, the paths for transmitting different pieces of metadata of incoming packets are identified in the network switch. Once the metadata paths are identified, the proposed approach identifies the timing constraints that the metadata paths need to satisfy in order for the network switch to function properly. The proposed approach then calculates the current delays of the metadata paths and determines optimal timing values of each of the metadata paths in order to meet the timing constraints. The optimal timing values of the metadata paths are then compared to the current delays of the metadata paths to identify the paths which current delay values need to be adjusted.

Abstract: An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip. A signature of these flip-flop implemented registers on the semiconductor chip is periodically captured. The signature allows for the integrity of the flip-flop implemented registers to be constantly monitored. A soft error occurring on any of the flip-flop implemented registers can be immediately detected. In response to the detection, an interrupt is raised to notify software to take action.

Abstract: A method includes constructing a graph characterizing a set of packet headers associated with network traffic. The graph has a unique identifier for each possible combination of packet headers forming a path in the graph. A received packet is associated with a unique identifier in the graph. Characteristics of the received packet are reconstructed based upon the unique identifier.

Abstract: A quaternary content-addressable memory includes multiple entries configured to match a lookup word, with each of these entries including multiple cells and with the lookup word including multiple lookup bits for matching corresponding cells of each of the entries. Each of the cells is individually configurable to be in one of multiple states identified by two bits, with these states including a first matching state for matching a value of a corresponding bit of the lookup word with the value having a first matching value, a second matching state for matching the value of the corresponding bit having a second matching value, a wildcard state for matching the value of the corresponding bit having either the first or the second matching value, and an ignore state for indicating to ignore the cell in determining whether or not the entry to which the cell belongs matches the lookup word.