Abstract: Circuit and method for resetting clock circuitry. The circuit includes a chain of cascading units, each of which receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams. A chain of dividers provides one or more divided clock signals to the cascading units, wherein the divided clock signals are based on a gated common clock signal. An asynchronous reset signal is delivered to the dividers, and when asserted sets the dividers to a reset state. A clock source provides an ungated common clock signal. A clock gating circuit generates the gated common clock signal based on the ungated common clock signal, and is configured to hold the gated common clock signal while the asynchronous reset signal is asserted. The clock gating circuit provides the gated common clock signal to the dividers when the asynchronous reset signal is de-asserted.

Abstract: Circuit and method for resetting clock circuitry. The circuit includes a chain of cascading units, each of which receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams. A chain of dividers provides one or more divided clock signals to the cascading units, wherein the divided clock signals are based on a gated common clock signal. An asynchronous reset signal is delivered to the dividers, and when asserted sets the dividers to a reset state. A clock source provides an ungated common clock signal. A clock gating circuit generates the gated common clock signal based on the ungated common clock signal, and is configured to hold the gated common clock signal while the asynchronous reset signal is asserted. The clock gating circuit provides the gated common clock signal to the dividers when the asynchronous reset signal is de-asserted.

Abstract: Sidetone in a four-wire telephone station set that is coupled to a two-wire telephone line through a four-to-two wire hybrid circuit is automatically and cancel the phase "to a predetermined value", set by incrementally adjusting a balancing impedance connected to the circuit until an optimum impedance match between the telephone set and line is achieved. Under software control, during idle intervals between dialed digits when a call is initiated, a microcontroller mutes the telephone transmitter and receiver on the telephone side of the circuit and substitutes for these components a tone signal generator to produce a sidetone signal that is applied to a full-wave rectifier and therefrom to a peak voltage detector to generate a sidetone envelope. Individual ones of several impedance balancing networks are then sequentially connected to the telephone side of the circuit and the sidetone envelope for each balancing impedance is digitally encoded and stored.