Patents by Inventor Guy Jacob
Guy Jacob has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250136756Abstract: A method for synthesising polyepichlorohydrin including: a) reacting epichlorohydrin with boron trifluoroetherate in the presence of a polymerisation initiator; b) adding a good solvent for epichlorohydrin to the reaction product obtained in step a); c) adding epichlorohydrin to the reaction product obtained in step b).Type: ApplicationFiled: September 21, 2022Publication date: May 1, 2025Applicant: EURENCOInventors: Geneviève ECK, Thibaud ALAIME, Sergei KOSTJUK, François GANACHAUD, Guy JACOB
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Publication number: 20240419956Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: June 21, 2024Publication date: December 19, 2024Applicant: Intel CorporationInventors: Eran Ben-Avi, Neta Zmora, Guy Jacob, Lev Faivishevsky, Jeremie Dreyfuss, Tomer Bar-On, Jacob Subag, Yaniv Fais, Shira Hirsch, Orly Weisel, Zigi Walter, Yarden Oren
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Publication number: 20240392067Abstract: A method for synthesising polyepichlorohydrin includes: a) reacting epichlorohydrin with boron trifluoroetherate in the presence of a solvent; b) adding epichlorohydrin to the reaction product obtained in step a); c) hydrolysing the product obtained in step b).Type: ApplicationFiled: September 21, 2022Publication date: November 28, 2024Applicant: EURENCOInventors: Geneviève ECK, Thibaud ALAIME, Sergei KOSTJUK, François GANACHAUD, Guy JACOB
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Patent number: 12033063Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 24, 2023Date of Patent: July 9, 2024Assignee: Intel CorporationInventors: Eran Ben-Avi, Neta Zmora, Guy Jacob, Lev Faivishevsky, Jeremie Dreyfuss, Tomer Bar-On, Jacob Subag, Yaniv Fais, Shira Hirsch, Orly Weisel, Zigi Walter, Yarden Oren
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Publication number: 20240112033Abstract: In an example, an apparatus comprises at least one execution platform; and logic, at least partially including hardware logic, to receive a trained neural network model in a model optimizer and convert the trained neural network model to an optimized model comprising parameters that are fit to the at least one execution platform. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: November 20, 2023Publication date: April 4, 2024Applicant: Intel CorporationInventors: Amit Bleiweiss, Itamar Ben-Ari, Michael Behar, Guy Jacob, Gal Leibovich, Jacob Subag, Lev Faivishevsky, Yaniv Fais, Tomer Schwartz
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Publication number: 20230281435Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 24, 2023Publication date: September 7, 2023Applicant: Intel CorporationInventors: Eran Ben-Avi, Neta Zmora, Guy Jacob, Lev Faivishevsky, Jeremie Dreyfuss, Tomer Bar-On, Jacob Subag, Yaniv Fais, Shira Hirsch, Orly Weisel, Zigi Walter, Yarden Oren
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Patent number: 11656846Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: GrantFiled: November 24, 2020Date of Patent: May 23, 2023Assignee: INTEL CORPORATIONInventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
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Publication number: 20230154571Abstract: A selection process is iterative and includes an initialization associating with a so-called current molecule a value of a predetermined molecule descriptor associated with the target molecular structure, and during each iteration of the selection process, the process includes evaluating, for each molecule of a database including a plurality of molecules each associated with a value of the descriptor, a so-called overall similarity measure between the value of the descriptor associated with the molecule and the value of the descriptor associated with the current molecule; selecting molecules from the database having an overall similarity measure greater than a predetermined threshold, the selected molecules being added to the reference subset; and updating the value of the descriptor associated with the current molecule from the values of the descriptors associated with at least some of the molecules belonging to the reference subset.Type: ApplicationFiled: June 22, 2018Publication date: May 18, 2023Inventors: Raphaël TERREUX, Charlotte ALLIOD, Roland DENIS, Guy JACOB
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Patent number: 11599777Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 28, 2017Date of Patent: March 7, 2023Assignee: Intel CorporationInventors: Eran Ben-Avi, Neta Zmora, Guy Jacob, Lev Faivishevsky, Jeremie Dreyfuss, Tomer Bar-On, Jacob Subag, Yaniv Fais, Shira Hirsch, Orly Weisel, Zigi Walter, Yarden Oren
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Patent number: 11600035Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 10, 2022Date of Patent: March 7, 2023Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
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Publication number: 20220237850Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 10, 2022Publication date: July 28, 2022Applicant: Intel CorporationInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
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Patent number: 11250610Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: GrantFiled: August 28, 2020Date of Patent: February 15, 2022Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
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Publication number: 20210141604Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: November 24, 2020Publication date: May 13, 2021Applicant: Intel CorporationInventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
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Publication number: 20210049804Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 28, 2020Publication date: February 18, 2021Applicant: Intel CorporationInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
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Patent number: 10882795Abstract: A process for manufacturing a composite part includes introducing an adhesion promoter into the pores of a fibrous preform formed by threads covered with a coating having —OH groups on its surface, the adhesion promoter including an electron-withdrawing group G1 that is reactive according to a reaction of substitution or of nucleophilic addition with the —OH groups, and a reactive group G2; grafting the adhesion promoter to the surface of the coating by a reaction of substitution or nucleophilic addition of the —OH groups on the group G1; introducing a ceramic precursor resin into the pores of the fibrous preform; polymerizing the resin introduced and bonding the grafted adhesion promoter to the resin by chemical reaction between these two compounds at the level of the group G2, and forming a ceramic matrix phase in the pores of the fibrous preform by pyrolysis of the polymerized resin.Type: GrantFiled: June 13, 2018Date of Patent: January 5, 2021Assignees: SAFRAN CERAMICS, ARIANEGROUP SASInventors: Nicolas Eberling-Fux, Eric Bouillon, Guy Jacob, Eddy Goullianne
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Patent number: 10853035Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: GrantFiled: March 27, 2020Date of Patent: December 1, 2020Assignee: INTEL CORPORATIONInventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
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Publication number: 20200293282Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: March 27, 2020Publication date: September 17, 2020Applicant: Intel CorporationInventors: YANIV Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
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Patent number: 10762685Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: GrantFiled: October 31, 2019Date of Patent: September 1, 2020Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
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Publication number: 20200143579Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: October 31, 2019Publication date: May 7, 2020Applicant: Intel CorporationInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
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Publication number: 20200131090Abstract: A process for manufacturing a composite part includes introducing an adhesion promoter into the pores of a fibrous preform formed by threads covered with a coating having —OH groups on its surface, the adhesion promoter including an electron-withdrawing group G1 that is reactive according to a reaction of substitution or of nucleophilic addition with the —OH groups, and a reactive group G2; grafting the adhesion promoter to the surface of the coating by a reaction of substitution or nucleophilic addition of the —OH groups on the group G1; introducing a ceramic precursor resin into the pores of the fibrous preform; polymerizing the resin introduced and bonding the grafted adhesion promoter to the resin by chemical reaction between these two compounds at the level of the group G2, and forming a ceramic matrix phase in the pores of the fibrous preform by pyrolysis of the polymerized resin.Type: ApplicationFiled: June 13, 2018Publication date: April 30, 2020Inventors: Nicolas EBERLING-FUX, Eric BOUILLON, Guy JACOB, Eddy GOUILLIANNE