Patents by Inventor Guy Jacob

Guy Jacob has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250136756
    Abstract: A method for synthesising polyepichlorohydrin including: a) reacting epichlorohydrin with boron trifluoroetherate in the presence of a polymerisation initiator; b) adding a good solvent for epichlorohydrin to the reaction product obtained in step a); c) adding epichlorohydrin to the reaction product obtained in step b).
    Type: Application
    Filed: September 21, 2022
    Publication date: May 1, 2025
    Applicant: EURENCO
    Inventors: Geneviève ECK, Thibaud ALAIME, Sergei KOSTJUK, François GANACHAUD, Guy JACOB
  • Publication number: 20240419956
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 21, 2024
    Publication date: December 19, 2024
    Applicant: Intel Corporation
    Inventors: Eran Ben-Avi, Neta Zmora, Guy Jacob, Lev Faivishevsky, Jeremie Dreyfuss, Tomer Bar-On, Jacob Subag, Yaniv Fais, Shira Hirsch, Orly Weisel, Zigi Walter, Yarden Oren
  • Publication number: 20240392067
    Abstract: A method for synthesising polyepichlorohydrin includes: a) reacting epichlorohydrin with boron trifluoroetherate in the presence of a solvent; b) adding epichlorohydrin to the reaction product obtained in step a); c) hydrolysing the product obtained in step b).
    Type: Application
    Filed: September 21, 2022
    Publication date: November 28, 2024
    Applicant: EURENCO
    Inventors: Geneviève ECK, Thibaud ALAIME, Sergei KOSTJUK, François GANACHAUD, Guy JACOB
  • Patent number: 12033063
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: July 9, 2024
    Assignee: Intel Corporation
    Inventors: Eran Ben-Avi, Neta Zmora, Guy Jacob, Lev Faivishevsky, Jeremie Dreyfuss, Tomer Bar-On, Jacob Subag, Yaniv Fais, Shira Hirsch, Orly Weisel, Zigi Walter, Yarden Oren
  • Publication number: 20240112033
    Abstract: In an example, an apparatus comprises at least one execution platform; and logic, at least partially including hardware logic, to receive a trained neural network model in a model optimizer and convert the trained neural network model to an optimized model comprising parameters that are fit to the at least one execution platform. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: November 20, 2023
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Amit Bleiweiss, Itamar Ben-Ari, Michael Behar, Guy Jacob, Gal Leibovich, Jacob Subag, Lev Faivishevsky, Yaniv Fais, Tomer Schwartz
  • Publication number: 20230281435
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: February 24, 2023
    Publication date: September 7, 2023
    Applicant: Intel Corporation
    Inventors: Eran Ben-Avi, Neta Zmora, Guy Jacob, Lev Faivishevsky, Jeremie Dreyfuss, Tomer Bar-On, Jacob Subag, Yaniv Fais, Shira Hirsch, Orly Weisel, Zigi Walter, Yarden Oren
  • Patent number: 11656846
    Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: May 23, 2023
    Assignee: INTEL CORPORATION
    Inventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
  • Publication number: 20230154571
    Abstract: A selection process is iterative and includes an initialization associating with a so-called current molecule a value of a predetermined molecule descriptor associated with the target molecular structure, and during each iteration of the selection process, the process includes evaluating, for each molecule of a database including a plurality of molecules each associated with a value of the descriptor, a so-called overall similarity measure between the value of the descriptor associated with the molecule and the value of the descriptor associated with the current molecule; selecting molecules from the database having an overall similarity measure greater than a predetermined threshold, the selected molecules being added to the reference subset; and updating the value of the descriptor associated with the current molecule from the values of the descriptors associated with at least some of the molecules belonging to the reference subset.
    Type: Application
    Filed: June 22, 2018
    Publication date: May 18, 2023
    Inventors: Raphaël TERREUX, Charlotte ALLIOD, Roland DENIS, Guy JACOB
  • Patent number: 11599777
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: March 7, 2023
    Assignee: Intel Corporation
    Inventors: Eran Ben-Avi, Neta Zmora, Guy Jacob, Lev Faivishevsky, Jeremie Dreyfuss, Tomer Bar-On, Jacob Subag, Yaniv Fais, Shira Hirsch, Orly Weisel, Zigi Walter, Yarden Oren
  • Patent number: 11600035
    Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: March 7, 2023
    Assignee: INTEL CORPORATION
    Inventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
  • Publication number: 20220237850
    Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: February 10, 2022
    Publication date: July 28, 2022
    Applicant: Intel Corporation
    Inventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
  • Patent number: 11250610
    Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: February 15, 2022
    Assignee: INTEL CORPORATION
    Inventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
  • Publication number: 20210141604
    Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 13, 2021
    Applicant: Intel Corporation
    Inventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
  • Publication number: 20210049804
    Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: August 28, 2020
    Publication date: February 18, 2021
    Applicant: Intel Corporation
    Inventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
  • Patent number: 10882795
    Abstract: A process for manufacturing a composite part includes introducing an adhesion promoter into the pores of a fibrous preform formed by threads covered with a coating having —OH groups on its surface, the adhesion promoter including an electron-withdrawing group G1 that is reactive according to a reaction of substitution or of nucleophilic addition with the —OH groups, and a reactive group G2; grafting the adhesion promoter to the surface of the coating by a reaction of substitution or nucleophilic addition of the —OH groups on the group G1; introducing a ceramic precursor resin into the pores of the fibrous preform; polymerizing the resin introduced and bonding the grafted adhesion promoter to the resin by chemical reaction between these two compounds at the level of the group G2, and forming a ceramic matrix phase in the pores of the fibrous preform by pyrolysis of the polymerized resin.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: January 5, 2021
    Assignees: SAFRAN CERAMICS, ARIANEGROUP SAS
    Inventors: Nicolas Eberling-Fux, Eric Bouillon, Guy Jacob, Eddy Goullianne
  • Patent number: 10853035
    Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: December 1, 2020
    Assignee: INTEL CORPORATION
    Inventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
  • Publication number: 20200293282
    Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: YANIV Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
  • Patent number: 10762685
    Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 1, 2020
    Assignee: INTEL CORPORATION
    Inventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
  • Publication number: 20200143579
    Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 7, 2020
    Applicant: Intel Corporation
    Inventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
  • Publication number: 20200131090
    Abstract: A process for manufacturing a composite part includes introducing an adhesion promoter into the pores of a fibrous preform formed by threads covered with a coating having —OH groups on its surface, the adhesion promoter including an electron-withdrawing group G1 that is reactive according to a reaction of substitution or of nucleophilic addition with the —OH groups, and a reactive group G2; grafting the adhesion promoter to the surface of the coating by a reaction of substitution or nucleophilic addition of the —OH groups on the group G1; introducing a ceramic precursor resin into the pores of the fibrous preform; polymerizing the resin introduced and bonding the grafted adhesion promoter to the resin by chemical reaction between these two compounds at the level of the group G2, and forming a ceramic matrix phase in the pores of the fibrous preform by pyrolysis of the polymerized resin.
    Type: Application
    Filed: June 13, 2018
    Publication date: April 30, 2020
    Inventors: Nicolas EBERLING-FUX, Eric BOUILLON, Guy JACOB, Eddy GOUILLIANNE