Abstract: Provided are systems, apparatuses, and techniques for managing processor system power and performance based on operational metrics, hardware capabilities, and/or other parameters.

Abstract: There may be provided a method for traffic control in a network on chip (NOC), the method may include receiving, by input interface units of the NOC, flow control units destined to output interface units of the NOC; wherein multiple routing paths span between the input interface units and the output interface units; wherein at least some of the routing paths are formed by multiple routers of a grid of routers of the NOC and have a single turning point; allocating virtual channels to the flow control units, wherein an allocating of a virtual channel to a flow control unit (FCU) is based on a type of a transaction associated with the FCU and on a location of the single turning point; and routing the flow control units, based on the virtual channels allocated to the FCUs, between the input interface units and the output interface units.

Abstract: A data plane integrated circuit that includes interfacing units (IFUs), Datapath units (DPUs); and a network on chip (NoC). The DPUs are arranged in local sets of DPUs that are proximate to each other, each local set is configured to (a) store an instance of packet header processing control data structures and (b) independently perform local packet header processing and transmission scheduling.

Abstract: An elastic memory system that may include memory banks, clients that are configured to obtain access requests associated with input addresses; first address converters that are configured to convert the input addresses to intermediate addresses within a linear address space; address scramblers that are configured to convert the intermediate addresses to physical addresses while balancing a load between the memory banks; atomic operation units; an interconnect that is configured to receive modified access requests that are associated with the physical addresses, and send the modified access requests downstream, wherein atomic modified access requests are sent to the atomic operation units; wherein the atomic operations units are configured to execute the atomic modified access requests; wherein the memory banks are configured to respond to the atomic modified access requests and to non-atomic modified access requests.

Abstract: A modular switch and a method that includes (a) first tier switching elements that comprise input output (IO) ports; and (b) second tier switching elements that are coupled to the first tier switching elements in a non-blocking manner. The first tier switching elements are configured to perform traffic management of traffic, and perform substantially all egress processing and ingress processing of the traffic; wherein the traffic management comprises load balancing, traffic shaping and flow-based reordering. The second tier switching elements are configured to (a) provide a shared memory space to the first tier switching elements, (b) perform substantially all of the queuing of traffic and (c) send, to the first tier switching elements, status information related to the status of shared memory resources. The first tier switching elements are configured to perform the traffic management based, at least in part, on the status information.

Abstract: Causal explanations of outputs of a neural network can be learned from an attention layer in the neural network. The neural network may compute an output variable by processing a variable set including one or more input variables. An attention matrix may be computed by the attention layer in an abductive inference for which a new variable set including the input variables and the output variable is input into the neural network. Causal relationship between the variables in the new variable set may be determined based on the attention matrix and illustrated in a causal graph. A tree structure may be generated based on the causal graph. An input variable may be identified using the tree structure and determined to be the reason why the neural network computed the output variable. An explanation of the causal relation between the input variable and output variable can be generated and provided.

Abstract: Various embodiments are generally directed to techniques for determining artificial neural network topologies, such as by utilizing probabilistic graphical models, for instance. Some embodiments are particularly related to determining neural network topologies by bootstrapping a graph, such as a probabilistic graphical model, into a multi-graphical model, or graphical model tree. Various embodiments may include logic to determine a collection of sample sets from a dataset. In various such embodiments, each sample set may be drawn randomly for the dataset with replacement between drawings. In some embodiments, logic may partition a graph into multiple subgraph sets based on each of the sample sets. In several embodiments, the multiple subgraph sets may be scored, such as with Bayesian statistics, and selected amongst as part of determining a topology for a neural network.

Abstract: A system for managing traffic between servers, the system may include first tier switches that are coupled to the servers; second tier switches that are coupled to the first tier switches and to third tier switches; and controllers. Wherein each first tier switch comprises first queues. Wherein each second tier switch comprises second queues. The controllers are configured to control a traffic between the first tier switches and the second tier switches attributed to the traffic between the servers, (a) on, at least, a queue granularity; (b) while controlling some first queues to provide buffer extension to some second queues, and (c) while controlling some second queues to provide buffer extension to some first queues.

Abstract: A mechanism is described for facilitating learning and application of neural network topologies in machine learning at autonomous machines. A method of embodiments, as described herein, includes monitoring and detecting structure learning of neural networks relating to machine learning operations at a computing device having a processor, and generating a recursive generative model based on one or more topologies of one or more of the neural networks. The method may further include converting the generative model into a discriminative model.

Abstract: A method for managing traffic in a computerized system that may include routers and at least one edge device, the method may include performing traffic management operations for controlling traffic related to the routers while executing a first traffic management operations by the at least one edge device, and executing second traffic management operations by the routers.

Abstract: A mechanism is described for facilitating learning and application of neural network topologies in machine learning at autonomous machines. A method of embodiments, as described herein, includes monitoring and detecting structure learning of neural networks relating to machine learning operations at a computing device having a processor, and generating a recursive generative model based on one or more topologies of one or more of the neural networks. The method may further include converting the generative model into a discriminative model.

Abstract: An elastic memory system that may include memory banks, clients that are configured to obtain access requests associated with input addresses; first address converters that are configured to convert the input addresses to intermediate addresses within a linear address space; address scramblers that are configured to convert the intermediate addresses to physical addresses while balancing a load between the memory banks; atomic operation units; an interconnect that is configured to receive modified access requests that are associated with the physical addresses, and send the modified access requests downstream, wherein atomic modified access requests are sent to the atomic operation units; wherein the atomic operations units are configured to execute the atomic modified access requests; wherein the memory banks are configured to respond to the atomic modified access requests and to non-atomic modified access requests.

Abstract: A method and a high-frequency module that includes a high frequency die that may include multiple die pads; a substrate that may include a first buildup layer, a second buildup layer and a core that is positioned between the first buildup layer and a second buildup layer; a line card that may include multiple line card pads; and multiple conductors that pass through the substrate without reaching a majority of a depth of the core, and couple the multiple die pads to the multiple line card pads.

Abstract: A method for responding to a failure of a main die of a switch data-plane device, the method may include applying a secondary packet forwarding process by multiple chiplets, following the failure of the main die and during at least a part of an execution of a synchronous graceful process that follows the failure of the main die; wherein the multiple chiplets are interconnected to each other by a secondary interconnect; wherein the multiple chiplets and are coupled to the main die by a primary interconnect; wherein the applying of the secondary packet forwarding process is less complex than a primary forwarding process applied by the main die while the main die is functional.

Abstract: A system for managing traffic between servers, the system may include first tier switches that are coupled to the servers; second tier switches that are coupled to the first tier switches and to third tier switches; and controllers. Wherein each first tier switch comprises first queues. Wherein each second tier switch comprises second queues. The controllers are configured to control a traffic between the first tier switches and the second tier switches attributed to the traffic between the servers, (a) on, at least, a queue granularity; (b) while controlling some first queues to provide buffer extension to some second queues, and (c) while controlling some second queues to provide buffer extension to some first queues.

Abstract: A method and a high-frequency module that includes a high frequency die that may include multiple die pads; a substrate that may include a first buildup layer, a second buildup layer and a core that is positioned between the first buildup layer and a second buildup layer; a line card that may include multiple line card pads; and multiple conductors that pass through the substrate without reaching a majority of a depth of the core, and couple the multiple die pads to the multiple line card pads.

Abstract: A recursive method and apparatus produce a deep convolution neural network (CNN). The method iteratively processes an input directed acyclic graph (DAG) representing an initial CNN, a set of nodes, a set of exogenous nodes, and a resolution based on the CNN. An iteration for a node may include recursively performing the iteration upon each node in a descendant node set to create a descendant DAG, and upon each node in ancestor node sets to create ancestor DAGs, the ancestor node sets being a remainder of nodes in the temporary DAG after removing nodes of the descendent node set. The descendant and ancestor DAGs are merged, and a latent layer is created that includes a latent node for each ancestor node set. Each latent node is set to be a parent of sets of parentless nodes in a combined descendant DAG and ancestors DAGs before returning.

Abstract: A method and a high-frequency module that includes (a) a high frequency die that includes multiple die pads, (b) a substrate that comprises a first buildup layer, a second buildup layer and a core that is positioned between the first buildup layer and a second buildup layer, (c) a heat sink and coupling module that comprises a heat sink and multiple first conductors that pass through the heat sink and extend outside the heat sink; (d) a line card that comprises multiple line card pads that are coupled to external ends of the multiple first conductors; (e) coupling elements that are coupled to internal end of the multiple first conductors; and (f) multiple second conductors that pass through the substrate without reaching a majority of a depth of the core, and couple the multiple die pads to the coupling elements. The high frequency it not lower than fifty gigabits per second.

Abstract: A method and a high-frequency module that includes a high frequency die that may include multiple die pads; a substrate that may include a first buildup layer, a second buildup layer and a core that is positioned between the first buildup layer and a second buildup layer; a line card that may include multiple line card pads; and multiple conductors that pass through the substrate without reaching a majority of a depth of the core, and couple the multiple die pads to the multiple line card pads.

Abstract: A method and a high-frequency module that includes (a) a high frequency die that includes multiple die pads, (b) a substrate that comprises a first buildup layer, a second buildup layer and a core that is positioned between the first buildup layer and a second buildup layer, (c) a heat sink and coupling module that comprises a heat sink and multiple first conductors that pass through the heat sink and extend outside the heat sink; (d) a line card that comprises multiple line card pads that are coupled to external ends of the multiple first conductors; (e) coupling elements that are coupled to internal end of the multiple first conductors; and (f) multiple second conductors that pass through the substrate without reaching a majority of a depth of the core, and couple the multiple die pads to the coupling elements. The high frequency it not lower than fifty gigabits per second.