Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is removed and buffered in sidecar logic. While the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request.

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is removed and buffered in sidecar logic. While the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request.

Abstract: In a multithreaded data processing system including a plurality of processor cores and a system fabric, translation entries can be invalidated without deadlock. A processing unit forwards one or more translation invalidation requests received on the system fabric to a processor core via a non-blocking channel. Each of the translation invalidation requests specifies a respective target address and requests invalidation of any translation entry in the processor core that translates its respective target address.

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is removed and buffered in sidecar logic. While the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request.

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying and synchronization requests of a plurality of concurrently executing hardware threads are received in a shared queue. The plurality of storage-modifying requests includes a translation invalidation request of an initiating hardware thread, and the synchronization requests includes a synchronization request of the initiating hardware thread. The translation invalidation request is broadcast such that the translation invalidation request is received and processed by the plurality of processor cores to invalidate any translation entry that translates a target address of the translation invalidation request.

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests of a plurality of concurrently executing hardware threads are received in a shared queue. The storage-modifying requests include a translation invalidation request of an initiating hardware thread. The translation invalidation request is removed from the shared queue and buffered in sidecar logic in one of a plurality of sidecars each associated with a respective one of the plurality of hardware threads. While the translation invalidation request is buffered in the sidecar, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar.

Abstract: A processor core is supported by an upper level cache and a lower level cache that receives, from an interconnect fabric, a write injection request requesting injection of a partial cache line of data into a target cache line identified by a target real address. In response to receipt of the write injection request, a determination is made that the upper level cache is a highest point of coherency for the target real address. In response to the determination, the upper level cache and lower level cache collaborate to transfer the target cache line from the upper level cache to the lower level cache. The lower level cache updates the target cache line by merging the partial cache of data into the target cache line and storing the updated target cache line in the lower level cache.

Abstract: In at least some embodiments, a processor core generates one or more store operations by executing one or more store instructions in an instruction sequence. The one or more store operations are marked as a high priority store operations in response to detecting, in the instruction sequence, a window opening instruction and a window closing instruction bounding the one or more store instructions and are not so marked otherwise. The one or more store operations are buffered in a store queue associated with a cache memory of the processor core. Handling of the one or more store operations in the store queue is expedited in response to the one or more store operations being marked as high priority store operations and not expedited otherwise.

Abstract: In at least some embodiments, a processor core generates one or more store operations by executing one or more store instructions in an instruction sequence. The one or more store operations are marked as a high priority store operations in response to detecting, in the instruction sequence, a window opening instruction and a window closing instruction bounding the one or more store instructions and are not so marked otherwise. The one or more store operations are buffered in a store queue associated with a cache memory of the processor core. Handling of the one or more store operations in the store queue is expedited in response to the one or more store operations being marked as high priority store operations and not expedited otherwise.

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

Abstract: According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In response to receipt of the data prefetch request, the memory controller provides a coherency response indicating an excess number of data prefetch requests. In response to the coherency response, the particular processor core reduces a rate of issuance of data prefetch requests.

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

Abstract: In at least some embodiments, a processor core generates one or more store operations by executing one or more store instructions in an instruction sequence. The one or more store operations are marked as a high priority store operations in response to detecting, in the instruction sequence, a window opening instruction and a window closing instruction bounding the one or more store instructions and are not so marked otherwise. The one or more store operations are buffered in a store queue associated with a cache memory of the processor core. Handling of the one or more store operations in the store queue is expedited in response to the one or more store operations being marked as high priority store operations and not expedited otherwise.

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation operation in response to detecting, in the instruction sequence, a barrier instruction that precedes the store instruction in program order and that includes a field set to indicate the store operation should be accorded high priority and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation operation in response to detecting, in the instruction sequence, a barrier instruction that precedes the store instruction in program order and that includes a field set to indicate the store operation should be accorded high priority and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation in response to the store instruction being marked as high priority and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

Abstract: In at least some embodiments, a processor core generates one or more store operations by executing one or more store instructions in an instruction sequence. The one or more store operations are marked as a high priority store operations in response to detecting, in the instruction sequence, a window opening instruction and a window closing instruction bounding the one or more store instructions and are not so marked otherwise. The one or more store operations are buffered in a store queue associated with a cache memory of the processor core. Handling of the one or more store operations in the store queue is expedited in response to the one or more store operations being marked as high priority store operations and not expedited otherwise.

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation in response to the store instruction being marked as high priority and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.