Abstract: The disclosed embodiments relate to a system that generates a pseudorandom number. During operation, the system maintains a current dot-product for a thread, wherein the current dot-product is a dot-product between a pedigree for the thread and an array of coefficients, wherein the pedigree for the thread comprises an array of elements that specify a path to the thread from a root in a dynamic multi-threading hierarchy, and wherein the array of coefficients includes a coefficient for each level in the dynamic multi-threaded hierarchy. To generate the pseudorandom number, the system incrementally computes a new dot-product from the current dot-product without performing a multiplication operation by adding a coefficient associated with the thread's level in the dynamic multi-threading hierarchy to the current dot-product. Next, the system performs a mixing operation on the new dot-product to produce the pseudorandom number. Finally, the system updates the current dot-product to the new dot-product.

Abstract: The disclosed embodiments provide a system that facilitates the development and execution of a software program. During runtime of the software program, the system obtains a function call associated with an overloaded function and a generic type hierarchy. Next, the system determines an applicability of an implementation of the overloaded function to the function call. Finally, the system selects the implementation for invocation by the function call based on the determined applicability and a partial order of implementations for the overloaded function.

Abstract: The disclosed embodiments provide a system that facilitates the development and execution of a software program. During runtime of the software program, the system obtains a function call associated with an overloaded function and a generic type hierarchy that lacks contravariance. Next, the system determines an applicability of an implementation of the overloaded function to the function call. Finally, the system selects the implementation for invocation by the function call based on the determined applicability and a partial order of implementations for the overloaded function.

Abstract: The disclosed embodiments provide a system that facilitates the development and execution of a software program. During runtime of the software program, the system obtains a function call associated with an overloaded function and a generic type hierarchy that lacks contravariance. Next, the system determines an applicability of an implementation of the overloaded function to the function call. Finally, the system selects the implementation for invocation by the function call based on the determined applicability and a partial order of implementations for the overloaded function.

Abstract: The disclosed embodiments provide a system that facilitates the development and execution of a software program. During runtime of the software program, the system obtains a function call associated with an overloaded function and a generic type hierarchy. Next, the system determines an applicability of an implementation of the overloaded function to the function call. Finally, the system selects the implementation for invocation by the function call based on the determined applicability and a partial order of implementations for the overloaded function.

Abstract: One embodiment of the present invention provides a system that facilitates performing operations on a lock-free double-ended queue (deque). This deque is implemented as a doubly-linked list of nodes formed into a ring, so that node pointers in one direction form an inner ring, and node pointers in the other direction form an outer ring. The deque has an inner hat, which points to a node next to the last occupied node along the inner ring, and an outer hat, which points to a node next to the last occupied node along the outer ring. The system uses a double compare-and-swap (DCAS) operation while performing pop and push operations onto either end of the deque, as well as growing and shrinking operations to change the number of nodes that are in the ring used by the deque.

Abstract: In general, in one aspect, the invention relates to a method for integrating dimensional analysis in a program comprising defining a specific dimension class within the program, wherein the specific dimension class is an instance of the dimension meta-class, defining an instantiation of a unit class within the program, wherein the instantiation of the unit class comprises the specific dimension class as a type parameter associated with the instantiation of the unit class, defining a method within the program using the instantiation of the unit class and the specific dimension class, and compiling the program to generate an executable code corresponding to the program, wherein the program is written in an object-oriented language.

Abstract: A computer system implementing transient blocking synchronization allows a memory location leased by a first process to be read-accessible to another process. In other words, more than one thread may have read-only type leases on a given memory location at a given time. Such “shared” leases expire when respective lease periods of the shared leases elapse.

Abstract: A computer system uses transient blocking synchronization for performing operations on shared memory. When performing operations on more than one memory location, the computer system obtains transient exclusive access to a first memory location. The computer system then obtains transient exclusive access to a second memory location, where the transient exclusive access to the second memory location does not expire prior to an expiration of the transient exclusive access to the first memory location or until explicitly unleased.

Abstract: One embodiment of the present invention provides a system that facilitates importing static members of a class. During operation, the system examines code associated with a compilation unit to locate a static import declaration that identifies one or more static members of the class to import. Upon finding such a static import declaration, the system records the static import declaration in a symbol table used to compile the compilation unit. This allows the names for the one or more static members of the class to appear within the compilation unit without being prefixed with a name for the class.

Abstract: Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and a first input interval lower-point. Next, computing an output interval includes producing a second result from the conditional selection, the operands respectively including a second input interval upper-point, the first input interval upper-point, and the first input interval lower-point. Furthermore, computing an output interval includes producing a third result from a conditional division using the first operand, the second operand, and the third operand, the operands respectively including the first result, the second input interval upper-point, and the second input interval lower-point.

Abstract: One embodiment of the present invention provides a system that facilitates importing static members of a class. During operation, the system examines code associated with a compilation unit to locate a static import declaration that identifies one or more static members of the class to import. Upon finding such a static import declaration, the system records the static import declaration in a symbol table used to compile the compilation unit. This allows the names for the one or more static members of the class to appear within the compilation unit without being prefixed with a name for the class.

Abstract: A system and method for adding routing information for a node to a routing table, which efficiently makes necessary changes to the routing table to support routing to and from the node, while maintaining the deadlock-free quality of the paths described by the routing table. The routing table is generated by storing routing information in the routing table that reflects and describes a deadlock-free set of paths through a network of nodes. A row of entries is added to the routing table describing how to forward data units from the node. A column of entries is added to the routing table describing how to forward data units addressed to the node. The forwarding information within each entry added to the routing table maintains the deadlock-free quality of the set of paths represented by the forwarding table.

Abstract: A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. The result can condition the outcome of a floating point instruction.

Abstract: A system and method for calculating a deadlock-free set of paths in a network which generates an ordered set of deadlock-free sub-topologies, referred to as “layers.”The ordered set of layers is used to determine a deadlock-free set of paths through the network. The resulting paths allow data to be efficiently routed through the network without causing traffic to be disproportionately routed through any subset of links. Each of the deadlock-free layers may be any type of deadlock-free sub-topology. The generated ordering may be any arbitrary ordering of the layers. A shortest-path route calculation is performed with the following constraint: starting at any given layer, for each node, proceed to calculate a shortest path to every other node in the graph where at any node being utilized to assess a given minimum path, the path may move to any higher-ordered layer, but may never return to a lower ordered layer. In this way, within each layer, a path moves through a tree and thus avoids deadlock.

Abstract: A system for providing a floating point square root comprises an analyzer circuit configured to determine a first status of a first floating point operand based upon data within the first floating point operand. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the square root of the first floating point operand and a resulting status embedded within the resulting floating point operand.

Abstract: A system for providing a floating point product comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data within the second floating point operand respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the product of the first floating point operand and the second floating point operand. Additionally, the results circuit provides a resulting status embedded within the resulting floating point operand.

Abstract: A system for providing a floating point remainder comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and the second floating point operand, respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the remainder of the first floating point operand and the second floating point operand and a resulting status embedded within the resulting floating point operand.

Abstract: A system for providing a floating point division comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data within the second floating point operand respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the result of the division of the first floating point operand by the second floating point operand. Additionally, the results circuit provides resulting status embedded within the resulting floating point operand.

Abstract: A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined formats in which the plurality of operands are represented, and generates one or more control signals. The result assembler receives the control signals from the circuit, along with one or more inputs, and assembles a result.