Patents by Inventor Guy Lederman
Guy Lederman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240056380Abstract: In one embodiment, a multi-segment communication network system includes nodes connected via links, a first node including a first receiver and transmitter, and a second node including a second receiver and transmitter, wherein the first transmitter is to transmit a link training frame including a training pattern to the second receiver, which is to receive the link training frame, the second node is to find a tuning factor to which to tune the first transmitter responsively to the training pattern, and generate a request indicative of the found tuning factor, the second transmitter is to send the request in the link training frame via a plurality of the links to the first receiver, the first receiver is to receive the request, and the first node is to tune at least one parameter of the first transmitter based on the tuning factor indicated in the request.Type: ApplicationFiled: February 27, 2023Publication date: February 15, 2024Inventors: Zvi Rechtman, Guy Lederman, Stanislav Gurtovoy, Ran Ravid, Lavi Koch, Oded Nadir
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Publication number: 20240039689Abstract: In one embodiment, a retimer device includes a receiver to receive data from a first device via a data link, retimer circuitry to recover a clock phase from the received data, and prepare a new copy of the received data sampled by a clean clock based on the recovered clock phase, a transmitter to transmit the new copy to a second device via the data link, wherein the receiver is configured to receive an in-band standby signal from the first device having a given pattern in a physical layer of the signal, activate a power saving mode of the retimer device responsively to the standby signal having the given pattern in the physical layer of the standby signal, receive an in-band wakeup signal from the first device, and initiate an exit from the power saving mode to power up the retimer device responsively to the wakeup signal.Type: ApplicationFiled: November 27, 2022Publication date: February 1, 2024Inventors: Roman Meltser, Guy Lederman, Ran Ravid, Zvi Rechtman, Lavi Koch
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Patent number: 11764939Abstract: A method for communication in a network that includes multiple nodes having respective network interfaces and interconnects between the network interfaces, which include at least first and second network interfaces connected by a physical interconnect having a given latency. The method includes defining a target latency, greater than the given latency, for communication between the first and second network interfaces. Data are transmitted between the first and second network interfaces over the physical interconnect while applying, by at least one of the first and second network interfaces, a delay in transmission of the data corresponding to a difference between the target latency and the given latency.Type: GrantFiled: July 14, 2022Date of Patent: September 19, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Lion Levi, Guy Lederman
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Patent number: 11606157Abstract: A network node includes a port and circuitry. The port is configured for communicating over a packet network. The circuitry is configured to receive, via the port, a sequence of packets from a peer network node, the sequence of packets including (i) a time-protocol packet and (ii) a transmit-side (TX) time-stamp indicative of a time at which the time-protocol packet was transmitted from the peer network node, to assess a receive-side (RX) traffic pattern over one or more of the received packets in the sequence that precede reception of the time-protocol packet, and to calculate an accuracy measure for the TX time-stamp, based on the assessed RX traffic pattern.Type: GrantFiled: November 7, 2021Date of Patent: March 14, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Wojciech Wasko, Dotan David Levi, Guy Lederman
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Patent number: 11552871Abstract: In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.Type: GrantFiled: June 14, 2020Date of Patent: January 10, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ran Sela, Liron Mula, Ran Ravid, Guy Lederman, Dotan David Levi
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Patent number: 11336383Abstract: In certain exemplary embodiments, a switching device is provided, including an input interface configured to communicate with a packet source, an output interface configured to communicate with a packet destination, and packet processing circuitry. The packet processing circuitry is configured to receive a plurality of packets from the packet source via the input interface, each of the plurality of packets being associated with a packet descriptor, at least one of the packet descriptors being a transmission time packet descriptor including a desired physical transmission time for the packet associated with the transmission time packet descriptor, to receive an indication of a clock time, and for each packet associated with a transmission time packet descriptor, to physically transmit the packet associated with the transmission time packet descriptor, via the output interface, at a clock time corresponding to the desired physical transmission time. Related apparatus an methods are also provided.Type: GrantFiled: June 24, 2020Date of Patent: May 17, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Liron Mula, Dotan David Levi, Ran Ravid, Guy Lederman
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Publication number: 20210409137Abstract: In certain exemplary embodiments, a switching device is provided, including an input interface configured to communicate with a packet source, an output interface configured to communicate with a packet destination, and packet processing circuitry. The packet processing circuitry is configured to receive a plurality of packets from the packet source via the input interface, each of the plurality of packets being associated with a packet descriptor, at least one of the packet descriptors being a transmission time packet descriptor including a desired physical transmission time for the packet associated with the transmission time packet descriptor, to receive an indication of a clock time, and for each packet associated with a transmission time packet descriptor, to physically transmit the packet associated with the transmission time packet descriptor, via the output interface, at a clock time corresponding to the desired physical transmission time. Related apparatus an methods are also provided.Type: ApplicationFiled: June 24, 2020Publication date: December 30, 2021Inventors: Liron Mula, Dotan David Levi, Ran Ravid, Guy Lederman
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Publication number: 20210392065Abstract: In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.Type: ApplicationFiled: June 14, 2020Publication date: December 16, 2021Inventors: Ran Sela, Liron Mula, Ran Ravid, Guy Lederman, Dotan David Levi
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Patent number: 11157433Abstract: A Multi-Chip-Module (MCM) includes an MCM substrate and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate. The DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced date and durations of the first time periods and the second time periods, are preset.Type: GrantFiled: January 26, 2020Date of Patent: October 26, 2021Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Guy Lederman, Ran Ravid, Asaf Horev
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Publication number: 20210232525Abstract: A Multi-Chip-Module (MCM) includes an MCM substrate and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate. The DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced date and durations of the first time periods and the second time periods, are preset.Type: ApplicationFiled: January 26, 2020Publication date: July 29, 2021Inventors: Guy Lederman, Ran Ravid, Asaf Horev