Patents by Inventor Guy Lederman

Guy Lederman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260089380
    Abstract: Camera systems having integrated light sources are described. The camera system may include a printed circuit board, a camera module, a bracket, a first light source, and a set of electrical interconnects. The printed circuit board has a flexible portion and a rigid portion. The camera module is mounted to the rigid portion of the printed circuit board and includes a lens barrel. The first light source is mounted to a top surface of the bracket. The set of electrical interconnects are between the rigid portion of the printed circuit board and the bracket. The bracket at least partially surrounds the lens barrel. The bracket is mounted to at least the rigid portion of the printed circuit board. The first light source is electrically connected to the printed circuit board via the set of electrical interconnects.
    Type: Application
    Filed: August 12, 2025
    Publication date: March 26, 2026
    Inventors: Julien Vittu, Guy Lederman, Katya Gotlib, Yaron Gross, Rafi Ambar
  • Publication number: 20260081863
    Abstract: In one embodiment, a multi-segment communication network system includes nodes connected via links, a first node including a first receiver and transmitter, and a second node including a second receiver and transmitter, wherein the first transmitter is to transmit a link training frame including a training pattern to the second receiver, which is to receive the link training frame, the second node is to find a tuning factor to which to tune the first transmitter responsively to the training pattern, and generate a request indicative of the found tuning factor, the second transmitter is to send the request in the link training frame via a plurality of the links to the first receiver, the first receiver is to receive the request, and the first node is to tune at least one parameter of the first transmitter based on the tuning factor indicated in the request.
    Type: Application
    Filed: November 25, 2025
    Publication date: March 19, 2026
    Inventors: Zvi Rechtman, Guy Lederman, Stanislav Gurtovoy, Ran Ravid, Lavi Koch, Oded Nadir
  • Publication number: 20260074877
    Abstract: In one embodiment, a syntonization system includes a device including a dedicated clock signal input interface to be connected by a clock connection to a remote device and to receive a remote clock signal from the remote device, the remote device being external to the device, and clock circuitry to generate a local clock signal, and a digital clock controller to generate digital control signals to control the clock circuitry to syntonize the local clock signal according to the remote clock signal based on a difference between frequencies of the remote clock signal and the local clock signal, and provide the digital control signals to the clock circuitry, wherein the clock circuitry is to adjust the frequency of the local clock signal based on the digital control signals.
    Type: Application
    Filed: September 12, 2024
    Publication date: March 12, 2026
    Inventors: Natan Manevich, Bar Shapira, Nir Laufer, Dotan Levi, Ana-Maria Cretan, Asaf Horev, Guy Lederman, Yuri Chipchev, Dmitry Lachover
  • Publication number: 20260067110
    Abstract: A device or system including one or more devices is provided. In one example, a device includes one or more circuits that enable the device to determine that a communication link between a first communication node and a second communication node is in a link idle state. The device may further, in response to determining that the communication link is in the link idle state, transmit a disable command to one or both of the first communication node and the second communication node, where the disable command causes a recipient thereof to disable part of an encoding operation for the communication link.
    Type: Application
    Filed: August 30, 2024
    Publication date: March 5, 2026
    Inventors: Guy Lederman, Asaf Horev, Ran Ravid
  • Patent number: 12563511
    Abstract: A system including a device, coupled to a link and including a transmitter, generates a control block for synchronization via a physical layer of the link, the control block including a header portion of bits corresponding to a header indicating the message is a control block and a data portion of bits including synchronization information for synchronizing via the physical layer. The device interleaves the control block between two of a plurality of data blocks of a data packet, and transmits, via the link, the data packet and the control block.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: February 24, 2026
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ran Ravid, Guy Lederman, Liron Mula, Eitan Zahavi, Peter Paneah
  • Patent number: 12500830
    Abstract: In one embodiment, a multi-segment communication network system includes nodes connected via links, a first node including a first receiver and transmitter, and a second node including a second receiver and transmitter, wherein the first transmitter is to transmit a link training frame including a training pattern to the second receiver, which is to receive the link training frame, the second node is to find a tuning factor to which to tune the first transmitter responsively to the training pattern, and generate a request indicative of the found tuning factor, the second transmitter is to send the request in the link training frame via a plurality of the links to the first receiver, the first receiver is to receive the request, and the first node is to tune at least one parameter of the first transmitter based on the tuning factor indicated in the request.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: December 16, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Zvi Rechtman, Guy Lederman, Stanislav Gurtovoy, Ran Ravid, Lavi Koch, Oded Nadir
  • Patent number: 12418393
    Abstract: In one embodiment, a retimer device includes a receiver to receive data from a first device via a data link, retimer circuitry to recover a clock phase from the received data, and prepare a new copy of the received data sampled by a clean clock based on the recovered clock phase, a transmitter to transmit the new copy to a second device via the data link, wherein the receiver is configured to receive an in-band standby signal from the first device having a given pattern in a physical layer of the signal, activate a power saving mode of the retimer device responsively to the standby signal having the given pattern in the physical layer of the standby signal, receive an in-band wakeup signal from the first device, and initiate an exit from the power saving mode to power up the retimer device responsively to the wakeup signal.
    Type: Grant
    Filed: November 27, 2022
    Date of Patent: September 16, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Roman Meltser, Guy Lederman, Ran Ravid, Zvi Rechtman, Lavi Koch
  • Publication number: 20250279926
    Abstract: Systems, computer program products, and methods are described for efficient link-down management. An example transmitter detects an impending link-down event at the transmitter. Once detected, the transmitter encodes the link-down event within a control block. The encoded control block is then transmitted via a physical layer of the communication network to a receiver. Once the control block is transmitted, the transmitter then initiates the link-down event. An example receiver receives the control block via a physical layer of the communication network from a transmitter. Then, the receiver extracts, from the control block, an operational code (opcode) identifying an impending link-down event at the transmitter. In response, the receiver retrieves, from a database, a responsive action corresponding to the link-down event based on the extracted opcode and subsequently executes the responsive action.
    Type: Application
    Filed: March 4, 2024
    Publication date: September 4, 2025
    Applicant: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Gil GOLAN, Zvi RECHTMAN, Ran RAVID, Guy LEDERMAN, Asaf HOREV, Oded NADIR, Lavi KOCH, Andy RODAN
  • Publication number: 20250158739
    Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.
    Type: Application
    Filed: January 16, 2025
    Publication date: May 15, 2025
    Inventors: Asaf Horev, Ran Ravid, Guy Lederman, Roman Meltser
  • Patent number: 12244416
    Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: March 4, 2025
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Asaf Horev, Ran Ravid, Guy Lederman, Roman Meltser
  • Publication number: 20240373379
    Abstract: A system including an interconnect device coupled with one or more devices where the first device of the one or more devices is to transmit a control block for synchronization via a physical layer of a link coupled to the high-speed interconnect device, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating the control block is associated with time synchronization information. The interconnect device is to receive data, parse the data, determine the data is associated with the control block, determine a delay associated with the physical layer transmitting the control block and transmitting a signal responsive to receiving the control block and determining the delay.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 7, 2024
    Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Liron Mula, Ariel Almog, Bar Shapira, Guy Lederman
  • Publication number: 20240373380
    Abstract: A system including a device coupled with a link and including a transmitter. The device is to generate a first control block for synchronization via a physical layer of the link, the first control block including a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating to perform a synchronization handshake. The device is further to transmit, via the link, the first control block comprising the header portion set of bits and the data portion of bit.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 7, 2024
    Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Eitan Zahavi, Yuval Shpigelman, Guy Lederman, Liron Mula, Omer Shabtai
  • Publication number: 20240373378
    Abstract: A system including a device coupled with a link and including a transmitter. The device is to generate a control block for synchronization via a physical layer of the link, the control block including a header portion of bits corresponding to a header indicating the message is a control block and a data portion of bits including synchronization information for synchronizing via the physical layer. The device is further to transmit, via the link, the control block comprising the header portion of bits and the data portion of bits.
    Type: Application
    Filed: May 4, 2023
    Publication date: November 7, 2024
    Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ran Ravid, Guy Lederman, Liron Mula, Eitan Zahavi, Peter Paneah
  • Publication number: 20240333423
    Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Inventors: Asaf Horev, Ran Ravid, Guy Lederman, Roman Meltser
  • Publication number: 20240056380
    Abstract: In one embodiment, a multi-segment communication network system includes nodes connected via links, a first node including a first receiver and transmitter, and a second node including a second receiver and transmitter, wherein the first transmitter is to transmit a link training frame including a training pattern to the second receiver, which is to receive the link training frame, the second node is to find a tuning factor to which to tune the first transmitter responsively to the training pattern, and generate a request indicative of the found tuning factor, the second transmitter is to send the request in the link training frame via a plurality of the links to the first receiver, the first receiver is to receive the request, and the first node is to tune at least one parameter of the first transmitter based on the tuning factor indicated in the request.
    Type: Application
    Filed: February 27, 2023
    Publication date: February 15, 2024
    Inventors: Zvi Rechtman, Guy Lederman, Stanislav Gurtovoy, Ran Ravid, Lavi Koch, Oded Nadir
  • Publication number: 20240039689
    Abstract: In one embodiment, a retimer device includes a receiver to receive data from a first device via a data link, retimer circuitry to recover a clock phase from the received data, and prepare a new copy of the received data sampled by a clean clock based on the recovered clock phase, a transmitter to transmit the new copy to a second device via the data link, wherein the receiver is configured to receive an in-band standby signal from the first device having a given pattern in a physical layer of the signal, activate a power saving mode of the retimer device responsively to the standby signal having the given pattern in the physical layer of the standby signal, receive an in-band wakeup signal from the first device, and initiate an exit from the power saving mode to power up the retimer device responsively to the wakeup signal.
    Type: Application
    Filed: November 27, 2022
    Publication date: February 1, 2024
    Inventors: Roman Meltser, Guy Lederman, Ran Ravid, Zvi Rechtman, Lavi Koch
  • Patent number: 11764939
    Abstract: A method for communication in a network that includes multiple nodes having respective network interfaces and interconnects between the network interfaces, which include at least first and second network interfaces connected by a physical interconnect having a given latency. The method includes defining a target latency, greater than the given latency, for communication between the first and second network interfaces. Data are transmitted between the first and second network interfaces over the physical interconnect while applying, by at least one of the first and second network interfaces, a delay in transmission of the data corresponding to a difference between the target latency and the given latency.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: September 19, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Lion Levi, Guy Lederman
  • Patent number: 11606157
    Abstract: A network node includes a port and circuitry. The port is configured for communicating over a packet network. The circuitry is configured to receive, via the port, a sequence of packets from a peer network node, the sequence of packets including (i) a time-protocol packet and (ii) a transmit-side (TX) time-stamp indicative of a time at which the time-protocol packet was transmitted from the peer network node, to assess a receive-side (RX) traffic pattern over one or more of the received packets in the sequence that precede reception of the time-protocol packet, and to calculate an accuracy measure for the TX time-stamp, based on the assessed RX traffic pattern.
    Type: Grant
    Filed: November 7, 2021
    Date of Patent: March 14, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Wojciech Wasko, Dotan David Levi, Guy Lederman
  • Patent number: 11552871
    Abstract: In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.
    Type: Grant
    Filed: June 14, 2020
    Date of Patent: January 10, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Ran Sela, Liron Mula, Ran Ravid, Guy Lederman, Dotan David Levi
  • Patent number: 11336383
    Abstract: In certain exemplary embodiments, a switching device is provided, including an input interface configured to communicate with a packet source, an output interface configured to communicate with a packet destination, and packet processing circuitry. The packet processing circuitry is configured to receive a plurality of packets from the packet source via the input interface, each of the plurality of packets being associated with a packet descriptor, at least one of the packet descriptors being a transmission time packet descriptor including a desired physical transmission time for the packet associated with the transmission time packet descriptor, to receive an indication of a clock time, and for each packet associated with a transmission time packet descriptor, to physically transmit the packet associated with the transmission time packet descriptor, via the output interface, at a clock time corresponding to the desired physical transmission time. Related apparatus an methods are also provided.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: May 17, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Liron Mula, Dotan David Levi, Ran Ravid, Guy Lederman