Patents by Inventor Guy MOSHE
Guy MOSHE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11933661Abstract: A method for tracking non-homogeneous products on a shelf comprises monitoring weight measurement data points corresponding to the weight of the shelf and the products arranged thereupon, determining a set of weight-event parameters of a weight event, such as product identification and an action taken with respect to the product, and at least one of recording information about the results and displaying information about the results. A system for tracking non-homogeneous products on a shelf comprises processors for carrying out stored program instructions for carrying out the steps of the method.Type: GrantFiled: December 28, 2020Date of Patent: March 19, 2024Assignee: SHEKEL SCALES (2008) LTD.Inventors: Evyatar Yadai, Guy Moshe
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Publication number: 20220147614Abstract: Systems, methods, logic, and devices may support machine learning-based anomaly detections for embedded software applications. In a learning phase, an anomaly model training engine may construct an anomaly detection model, and the anomaly detection model configured to provide a determination of whether the embedded software application exhibits abnormal behavior based on activity measure and application parameter inputs. In a run-time phase, an anomaly detection engine may sample the embedded software application to obtain an activity measure and application parameters during the run-time execution and provide, as inputs to the anomaly detection model, the activity measure and the application parameters sampled during the run-time execution. The anomaly detection engine may further determine whether the embedded software application exhibits abnormal behavior based on an output from the anomaly detection model for the provided inputs.Type: ApplicationFiled: March 5, 2019Publication date: May 12, 2022Inventors: Yossi Veller, Guy Moshe
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Publication number: 20210148751Abstract: A method for tracking non-homogeneous products on a shelf comprises monitoring weight measurement data points corresponding to the weight of the shelf and the products arranged thereupon, determining a set of weight-event parameters of a weight event, such as product identification and an action taken with respect to the product, and at least one of recording information about the results and displaying information about the results. A system for tracking non-homogeneous products on a shelf comprises processors for carrying out stored program instructions for carrying out the steps of the method.Type: ApplicationFiled: December 28, 2020Publication date: May 20, 2021Inventors: Evyatar YADAI, Guy MOSHE
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Patent number: 8409974Abstract: A method of forming a semiconductor structure (and the resulting structure), includes straining a free-standing semiconductor, and fixing the strained, free-standing semiconductor to a substrate.Type: GrantFiled: August 20, 2009Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventors: Guy Moshe Cohen, Patricia May Mooney
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Patent number: 8053328Abstract: A method for depositing fine particles from a suspension on selected regions of a substrate is disclosed. The particles are deposited on selected regions of a clean hydrophobic semiconductor surface that are surrounded by a wetting boundary which includes a mesa formed by etching through a silicon-on-insulator (SOI) film and an underlying buried oxide of an SOI substrate. The process is well suited for the growth of semiconductor nanowires that nucleates from fine particle used as a catalyst.Type: GrantFiled: January 12, 2009Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventor: Guy Moshe Cohen
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Patent number: 7915685Abstract: A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.Type: GrantFiled: October 30, 2007Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventor: Guy Moshe Cohen
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Patent number: 7842562Abstract: A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.Type: GrantFiled: October 30, 2007Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventor: Guy Moshe Cohen
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Patent number: 7812340Abstract: A method of forming a semiconductor structure (and the resulting structure), includes straining a free-standing semiconductor, and fixing the strained, free-standing semiconductor to a substrate.Type: GrantFiled: June 13, 2003Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Guy Moshe Cohen, Patricia May Mooney
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Patent number: 7795677Abstract: Field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a FET is provided. The FET comprises a substrate having a silicon-on-insulator (SOI) layer which is divided into at least two sections electrically isolated from one another, one section included in a source region and the other section included in a drain region; a channel region connecting the source region and the drain region and including at least one nanowire; an epitaxial semiconductor material, grown from the SOI layer, covering the nanowire and attaching the nanowire to each section of the SOI layer; and a gate over the channel region.Type: GrantFiled: September 5, 2007Date of Patent: September 14, 2010Assignee: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy Moshe Cohen, Katherine Lynn Saenger
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Publication number: 20090309160Abstract: A method of forming a semiconductor structure (and the resulting structure), includes straining a free-standing semiconductor, and fixing the strained, free-standing semiconductor to a substrate.Type: ApplicationFiled: August 20, 2009Publication date: December 17, 2009Applicant: International Business Machines CorporationInventors: Guy Moshe Cohen, Patricia May Mooney
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Publication number: 20090216806Abstract: Personal digital assets are collected, managed, shared and archived on a social network using a client interface for registering a user and performing tasks. User sources are defined and assets are collected and organized chronologically as eternal Time-lines. Permission level rules are associated with each asset and Time-line and a plurality of subjective groups distinguished by their relation to the user are defined. Chosen assets of the Time-line are tagged with assigned keywords recognized by the social network service, thus sharing them with the tagged entity according to the permission level rules. Authorized members are invited to contribute and share assets with the founder of an established Time-line, and data storage is optimized in a way that every tag added to an assets appears on every instance it has on other Time-lines sharing that asset, such that shared assets are saved to the data storage only once.Type: ApplicationFiled: May 29, 2008Publication date: August 27, 2009Applicant: ALLOFME LTD.Inventors: Addy FEUERSTEIN, Tal YANIV, Oded YUNGER, Guy Moshe LEVITAN, Erez HUBERMAN
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Patent number: 7534675Abstract: Techniques for the fabrication of field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a method of fabricating a FET is provided comprising the following steps. A substrate is provided having a silicon-on-insulator (SOI) layer. At least one nanowire is deposited over the SOI layer. A sacrificial gate is formed over the SOI layer so as to cover a portion of the nanowire that forms a channel region. An epitaxial semiconductor material is selectively grown from the SOI layer that covers the nanowire and attaches the nanowire to the SOI layer in a source region and in a drain region. The sacrificial gate is removed. An oxide is formed that divides the SOI layer into at least two electrically isolated sections, one section included in the source region and the other section included in the drain region. A gate dielectric layer is formed over the channel region. A gate is formed over the channel region separated from the nanowire by the gate dielectric layer.Type: GrantFiled: September 5, 2007Date of Patent: May 19, 2009Assignee: International Business Machiens CorporationInventors: Sarunya Bangsaruntip, Guy Moshe Cohen, Katherine Lynn Saenger
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Publication number: 20090124092Abstract: A method for depositing fine particles from a suspension on selected regions of a substrate is disclosed. The particles are deposited on selected regions of a clean hydrophobic semiconductor surface that are surrounded by a wetting boundary which includes a mesa formed by etching through a silicon-on-insulator (SOI) film and an underlying buried oxide of an SOI substrate. The process is well suited for the growth of semiconductor nanowires that nucleates from fine particle used as a catalyst.Type: ApplicationFiled: January 12, 2009Publication date: May 14, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Guy Moshe Cohen
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Publication number: 20090061568Abstract: Techniques for the fabrication of field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a method of fabricating a FET is provided comprising the following steps. A substrate is provided having a silicon-on-insulator (SOI) layer. At least one nanowire is deposited over the SOI layer. A sacrificial gate is formed over the SOI layer so as to cover a portion of the nanowire that forms a channel region. An epitaxial semiconductor material is selectively grown from the SOI layer that covers the nanowire and attaches the nanowire to the SOI layer in a source region and in a drain region. The sacrificial gate is removed. An oxide is formed that divides the SOI layer into at least two electrically isolated sections, one section included in the source region and the other section included in the drain region. A gate dielectric layer is formed over the channel region. A gate is formed over the channel region separated from the nanowire by the gate dielectric layer.Type: ApplicationFiled: September 5, 2007Publication date: March 5, 2009Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy Moshe Cohen, Katherine Lynn Saenger
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Publication number: 20090057762Abstract: Field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a FET is provided. The FET comprises a substrate having a silicon-on-insulator (SOI) layer which is divided into at least two sections electrically isolated from one another, one section included in a source region and the other section included in a drain region; a channel region connecting the source region and the drain region and including at least one nanowire; an epitaxial semiconductor material, grown from the SOI layer, covering the nanowire and attaching the nanowire to each section of the SOI layer; and a gate over the channel region.Type: ApplicationFiled: September 5, 2007Publication date: March 5, 2009Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy Moshe Cohen, Katherine Lynn Saenger
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Patent number: 7498640Abstract: A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.Type: GrantFiled: May 15, 2003Date of Patent: March 3, 2009Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Kevin K. Chan, Guy Moshe Cohen, Kathryn Wilder Guarini, Christian Lavoie, Paul Michael Solomon, Ying Zhang
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Patent number: 7496251Abstract: Apparatus and methods for packaging optical communication devices include optical bench structures, such as silicon-optical benches (SiOB). An optical communications apparatus includes an optical bench comprising a substrate having an electrical turning via formed therein. An optoelectronic (OE) chip and integrated circuit (IC) chip are mounted on the optical bench and electrically connected using the electrical turning via. The electrical turning via extends in directions both perpendicular and transverse to a surface of the substrate such that the OE chip and IC chip can be mounted on perpendicular surfaces of the optical bench in close proximity and electrically connected using the electrical turning via.Type: GrantFiled: July 30, 2007Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Guy Moshe Cohen, Fuad Elias Doany, Jeannine M. Trewhella
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Publication number: 20090035919Abstract: A method for bonding microstructures to a semiconductor substrate using attractive forces, such as, hydrophobic, van der Waals, and covalent bonding is provided. The microstructures maintain their absolute position with respect to each other and translate vertically onto a wafer surface during the bonding process. The vertical translation of the micro-slabs is also referred to herein as “in-place bonding”. Semiconductor structures which include the attractively bonded microstructures and substrate are also disclosed.Type: ApplicationFiled: October 10, 2008Publication date: February 5, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy Moshe Cohen, Patricia M. Mooney, Vamsi K. Paruchuri
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Patent number: 7476573Abstract: A method for depositing fine particles from a suspension on selected regions of a substrate is disclosed. The particles are deposited on selected regions of a clean hydrophobic semiconductor surface that are surrounded by a wetting boundary which includes a mesa formed by etching through a silicon-on-insulator (SOI) film and an underlying buried oxide of an SOI substrate. The process is well suited for the growth of semiconductor nanowires that nucleates from fine particle used as a catalyst.Type: GrantFiled: May 23, 2005Date of Patent: January 13, 2009Assignee: International Business Machines CorporationInventor: Guy Moshe Cohen
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Publication number: 20080293246Abstract: A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.Type: ApplicationFiled: July 3, 2008Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy Moshe Cohen, Paul M. Solomon