Abstract: A power semiconductor package includes a power semiconductor die, a housing, a first lead, and a second lead. The housing includes a top side and a bottom side. The first lead is in contact with a first electrical contact of the power semiconductor die. Further, the first lead includes a heat exchanging portion on the top side of the housing and an electrical contact portion on the bottom side of the housing. At least 7.5 mm2 of the electrical contact portion of the first lead is available for contacting a printed circuit board. The second lead is in contact with a second electrical contact of the power semiconductor die. The second lead includes a heat exchanging portion on the bottom side of the housing and an electrical contact portion also on the bottom side of the housing.

Abstract: A power semiconductor package includes a power semiconductor die, a housing, a first lead, and a second lead. The housing includes a top side and a bottom side. The first lead is in contact with a first electrical contact of the power semiconductor die. Further, the first lead includes a heat exchanging portion on the top side of the housing and an electrical contact portion on the bottom side of the housing. At least 7.5 mm2 of the electrical contact portion of the first lead is available for contacting a printed circuit board. The second lead is in contact with a second electrical contact of the power semiconductor die. The second lead includes a heat exchanging portion on the bottom side of the housing and an electrical contact portion also on the bottom side of the housing.

Abstract: A totem pole power factor correction (PFC) converter is disclosed. The totem pole PFC converter includes a first transistor having a first current terminal coupled to a first node, a first control terminal, and a second current terminal. Also included is a second transistor having a third current terminal coupled to the second current terminal at a second node, a second control terminal, and a fourth current terminal coupled to a third node. A first rectifier is coupled to the first node and a first current sense resistor is coupled between the first rectifier and a fourth node. A second rectifier is coupled to the third node and a second current sense resistor coupled between the second rectifier and the fourth node. A current sense voltage for an analog controller is generated by current alternately flowing through the first current sense resistor and the second current sense resistor.