Patents by Inventor Guy Nakibly

Guy Nakibly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190215021
    Abstract: Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 11, 2019
    Inventors: Ofer Frishman, Erez Izenberg, Guy Nakibly
  • Patent number: 10298496
    Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to receive a first request for processing a first data packet associated with the queue identifier, and obtain a set of memory descriptors associated with the queue identifier from the memory. The set of descriptors can be stored in the cache. When a second request for processing a second data packet associated with the queue identifier is received, the cache control logic can determine that the cache is storing memory descriptors for processing the second data packet, and provide the memory descriptors used for processing the second packet.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 21, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Guy Nakibly, Benzi Denkberg, Erez Izenberg, Nafea Bshara, Uri Leder, Ofer Frishman
  • Publication number: 20190129796
    Abstract: A method for calculating a plurality (M) of redundancy blocks for multiple (N) data blocks of a plurality (D) of words each, the method comprises: receiving the number (M) of redundancy blocks by a calculator that comprises multiple (R) calculation units; configuring the calculator according to M and R; concurrently calculating, if M equals R, by the multiple (R) calculation units of the calculator, R sets of parity vectors, each set includes a plurality (D) of parity vectors; and calculating the plurality (M) of the redundancy blocks based on the R sets of parity vectors.
    Type: Application
    Filed: October 15, 2018
    Publication date: May 2, 2019
    Inventors: Ron Diamant, Nafea Bshara, Yaniv Shapira, Guy Nakibly
  • Patent number: 10255210
    Abstract: A master device transmits a transaction to a target device. The transaction includes a transaction identifier. An ordering message is sent to the target device over a bus that is different than a communication channel that the transaction is transmitted over. The ordering message includes the transaction identifier. The target device adjusts an order of execution of the transaction by the target device based at least in part on receiving the ordering message.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: April 9, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Nafea Bshara, Guy Nakibly, Adi Habusha
  • Patent number: 10228869
    Abstract: Techniques for controlling access to shared resources may include receiving multiple requests to access shared information associated with an identifier. For each of the requests, an entry in a linked list can be allocated to the request, and each entry can be associated with the identifier. The shared information associated with the identifier can be retrieved, and stored in each entry associated with the identifier. A conflict indicator is set in each entry to indicate whether the shared information is available for the request corresponding to the entry. The shared information stored in each entry is provided for each request after the conflict indicator in the corresponding entry indicates the shared information is available for the request.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: March 12, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Guy Nakibly, Benzi Denkberg, Ofer Frishman, Erez Izenberg, Uri Leder, Nafea Bshara
  • Patent number: 10198026
    Abstract: In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 5, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Guy Nakibly, Usama Nassir, Saar Gross, Nafea Bshara, Barak Wasserstrom, Daniel Joseph Grey
  • Patent number: 10177795
    Abstract: Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 8, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Ofer Frishman, Erez Izenberg, Guy Nakibly
  • Patent number: 10102072
    Abstract: A method for calculating a plurality (M) of redundancy blocks for multiple (N) data blocks of a plurality (D) of words each, the method comprises: receiving the number (M) of redundancy blocks by a calculator that comprises multiple (R) calculation units; configuring the calculator according to M and R; concurrently calculating, if M equals R, by the multiple (R) calculation units of the calculator, R sets of parity vectors, each set includes a plurality (D) of parity vectors; and calculating the plurality (M) of the redundancy blocks based on the R sets of parity vectors.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 16, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Nafea Bshara, Yaniv Shapira, Guy Nakibly
  • Patent number: 9934184
    Abstract: Provided are systems and methods for distributing ordering tasks in a computing system that includes master and target devices. In some implementations, a computing device is provided. The computing device may include a master device that is operable to initiate transactions. The computing device may further include a target device that is operable to receive transactions. In some implementations, the master device may be configured to transmit one or more transactions to the target device. The master device may further asynchronously indicate to the target device a number of transactions to execute. The master device may further asynchronously receive from the target device a number of transactions executed. The master device may then signal that at least one transaction from the one or more transactions it sent has completed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 3, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Guy Nakibly, Adi Habusha, Nafea Bshara, Itai Avron
  • Patent number: 9928207
    Abstract: Provided are systems and methods for generating transactions with a configurable port. In some implementations, a peripheral device is provided. The peripheral device comprises a configurable port. In some implementations, the configurable port may be configured to receive a first transaction. In these implementations, the first transactions may include an address. The address may include a transaction attribute. In some implementations, the configurable port may extract the transaction attribute and a transaction address from the address. The configurable port may further generate a second transaction that includes the transaction attribute and the transaction address. The configurable port may also transmit the second transaction.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 27, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Adi Habusha, Nafea Bshara, Itay Poleg, Erez Izenberg, Guy Nakibly, Matthew Shawn Wilson
  • Patent number: 9612611
    Abstract: In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: April 4, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Guy Nakibly, Usama Nassir, Saar Gross, Nafea Bshara, Barak Wasserstrom, Daniel Joseph Grey
  • Publication number: 20170091037
    Abstract: A method for calculating a plurality (M) of redundancy blocks for multiple (N) data blocks of a plurality (D) of words each, the method comprises: receiving the number (M) of redundancy blocks by a calculator that comprises multiple (R) calculation units; configuring the calculator according to M and R; concurrently calculating, if M equals R, by the multiple (R) calculation units of the calculator, R sets of parity vectors, each set includes a plurality (D) of parity vectors; and calculating the plurality (M) of the redundancy blocks based on the R sets of parity vectors.
    Type: Application
    Filed: September 30, 2016
    Publication date: March 30, 2017
    Inventors: Ron Diamant, Nafea Bshara, Yaniv Shapira, Guy Nakibly
  • Patent number: 9459958
    Abstract: A method for calculating a plurality (M) of redundancy blocks for multiple (N) data blocks of a plurality (D) of words each, the method comprises: receiving the number (M) of redundancy blocks by a calculator that comprises multiple (R) calculation units; configuring the calculator according to M and R; concurrently calculating, if M equals R, by the multiple (R) calculation units of the calculator, R sets of parity vectors, each set includes a plurality (D) of parity vectors; and calculating the plurality (M) of the redundancy blocks based on the R sets of parity vectors.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: October 4, 2016
    Inventors: Ron Diamant, Nafea Bshara, Yaniv Shapira, Guy Nakibly
  • Publication number: 20160098365
    Abstract: Techniques for emulating a configuration space by a peripheral device may include receiving a configuration access request, determining that the configuration access request is for a configuration space other than a native configuration space of the peripheral device, and retrieving an emulated configuration from an emulated configuration space. The configuration access request can then be serviced by using the emulated configuration.
    Type: Application
    Filed: October 1, 2015
    Publication date: April 7, 2016
    Inventors: Nafea Bshara, Adi Habusha, Guy Nakibly, Zorik Machulsky
  • Publication number: 20150154072
    Abstract: A method for calculating a plurality (M) of redundancy blocks for multiple (N) data blocks of a plurality (D) of words each, the method comprises: receiving the number (M) of redundancy blocks by a calculator that comprises multiple (R) calculation units; configuring the calculator according to M and R; concurrently calculating, if M equals R, by the multiple (R) calculation units of the calculator, R sets of parity vectors, each set includes a plurality (D) of parity vectors; and calculating the plurality (M) of the redundancy blocks based on the R sets of parity vectors.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 4, 2015
    Applicant: Annapurna Labs Ltd.
    Inventors: Ron Diamant, Nafea Bshara, Yaniv Shapira, Guy Nakibly
  • Patent number: 8963936
    Abstract: Aspects of the disclosure provide an apparatus. The apparatus includes a display module configured to display an image frame on a screen based on pixel data of the image frame, a memory chip configured to include a frame buffer that stores pixel data of image frames to be displayed by the display module and an integrated circuit, such as a system on chip (SOC). The integrated circuit includes a memory controller coupled to the memory chip and configured to access the memory chip to fetch the pixel data from the frame buffer in response to data requests, and a display controller coupled to the display module. The display controller is configured to send data requests to the memory controller to fetch the pixel data from the frame buffer and transmit the pixel data to the display module when the apparatus is in a first mode, such as an active mode.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: February 24, 2015
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Rabeeh Khoury, Dan Ilan, Guy Nakibly
  • Patent number: 8854542
    Abstract: Methods and systems for implementing video driving circuitry are disclosed. For example, in an embodiment, a system for driving a plurality of different types of video devices is disclosed. The system includes, for example, a System on a Chip (SoC) that itself includes a Liquid Crystal Display (LCD) controller circuit configured to generate digital video data, a first synchronization signal for controlling a first characteristic of the digital video data, and a second synchronization signal for controlling a second characteristic of the digital video data. The SoC further includes a delay circuit configured to variably delay the first synchronization signal and the second synchronization signal relative to the digital video data to generate a delayed first synchronization signal and a delayed second synchronization signal.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: October 7, 2014
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Dan Ilan, Guy Nakibly, Eilon Argov
  • Patent number: 8643781
    Abstract: Methods and systems for implementing video driving circuitry are disclosed. For example, in an embodiment, a system for driving a plurality of different types of video devices is disclosed. The system includes, for example, a System on a Chip (SoC) that itself includes a Liquid Crystal Display (LCD) controller circuit configured to generate digital video data, a first synchronization signal for controlling a first characteristic of the digital video data, and a second synchronization signal for controlling a second characteristic of the digital video data. The SoC further includes a delay circuit configured to variably delay the first synchronization signal and the second synchronization signal relative to the digital video data to generate a delayed first synchronization signal and a delayed second synchronization signal.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: February 4, 2014
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Dan Ilan, Guy Nakibly, Eilon Argov
  • Patent number: 8595441
    Abstract: Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for reducing the likelihood of cache line overlaps in a multi-processor system having a shared memory cache. A transformation function module coupled to the shared memory cache is configured to transform an index associated with a cache operation associated with a processor of the plurality of processors using a transformation function to generate a transformed index. In embodiments, groups of one or more processors have different or unique transformation functions associated with them in order to decrease the tendency or likelihood of their respective cache lines in the shared memory cache to overlap. Other embodiments are also described and claimed.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: November 26, 2013
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Guy Nakibly, Adi Habusha