Abstract: A thermal sensor for an integrated circuit including: a Proportional To Absolute Temperature (PTAT) circuit comprising n-type MOS transistors and providing a first voltage; and a voltage generator circuit comprising a p-type MOS transistor and providing a second voltage. A reference voltage is based on the first voltage and the second voltage. At least one thermal output signal is based on the reference voltage together with the first voltage and/or the second voltage. In another aspect, an integrated circuit has a power routing arrangement, providing a power supply core voltage (VDDCORE) to operate functional circuitry on the integrated circuit. One or more local thermal sensors are located on the integrated circuit, each comprising a PTAT circuit having MOS transistors using the power supply core voltage to generate a temperature-dependent voltage that varies independently of power supply core voltage variation.

Abstract: Glitch detection is provided for a clock signal in a semiconductor integrated circuit (IC), for example between an input buffer and a Phase Locked Loop (PLL). A first pulse signal is generated in response to a rising edge of the clock signal, and a second pulse signal is generated in response to its falling edge. A third pulse signal is generated at a predetermined period of time after a start of the first pulse signal, and a fourth pulse signal is generated at a predetermined period of time after a start of the second pulse signal. A glitch in the clock signal is indicated based on the third pulse signal having an opposite logical level to the clock signal, and/or based on the fourth pulse signal having the same logical level as the clock signal.

Abstract: A method including: Receiving timing data of multiple data paths of an integrated circuit (IC) design.

Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.

Abstract: An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

Abstract: Generation of a clock signal in a semiconductor integrated circuit (IC) is controlled using a Noise Modulation Agent (NMA), configured to measure the clock signal and output a parameter indicative of an effective cycle time of the clock signal. An Adaptive Frequency Scaling (AFS) circuit selectively adjusts a frequency of the clock signal, based on the output of the NMA indicating a change in a power supply voltage of the semiconductor IC.

Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.

Abstract: Loopback testing may be provided for one or more transmission output paths of a semiconductor Integrated Circuit (IC). One or more parametric loopback sensors are provided in the semiconductor IC, each parametric loopback sensor being configured to receive a clocked data input signal to a respective transmitter of the IC and a signal from a transmission output path from the respective transmitter of the IC, and to generate a respective sensor output based on a comparison of the clocked data input signal and the signal from the transmission output path for the respective transmitter of the IC. A programmable load circuit is also provided in the semiconductor IC, coupled to each transmission output path.

Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.

Abstract: An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

Abstract: An input/output (I/O) sensor is provided for a multi-IC (Integrated Circuit) module. The I/O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I/O block, an IC, and/or a multi-IC module.

Abstract: A memory circuit which includes: A synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines. A margin agent, determining a status of the synchronous memory cell array based on a time duration between a transition of the clock signal and a change on a signal derived from a bit line due to a signaling on at least one of the address lines. In another aspect, a memory cell, having a bit line configured to provide data input/output to the memory cell may be provided with a comparator, comparing a voltage on the bit line with a reference voltage and indicating of a status of the memory cell thereby. Firmware may receive the indication of the status of a memory cell array, and transmit the indication, issue an alert, and/or reconfigure the memory circuit responsive to the status.

Abstract: An I/O sensor including: a programmable delay line; a delayed sampling device having the following inputs: (a) a data signal that also serves as an input to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed sampling device and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.

Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.

Abstract: An I/O sensor including: a programmable delay line; a delayed clocked receiver having the following inputs: (a) a data signal and a reference voltage that also serve as inputs to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed clocked receiver and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.

Abstract: An I/O sensor including: a programmable delay line; a delayed clocked receiver having the following inputs: (a) a data signal and a reference voltage that also serve as inputs to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed clocked receiver and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.

Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.

Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.

Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.

Abstract: A thermal sensor for an integrated circuit including: a Proportional To Absolute Temperature (PTAT) circuit comprising n-type MOS transistors and providing a first voltage; and a voltage generator circuit comprising a p-type MOS transistor and providing a second voltage. A reference voltage is based on the first voltage and the second voltage. At least one thermal output signal is based on the reference voltage together with the first voltage and/or the second voltage. In another aspect, an integrated circuit has a power routing arrangement, providing a power supply core voltage (VDDcore) to operate functional circuitry on the integrated circuit. One or more local thermal sensors are located on the integrated circuit, each comprising a PTAT circuit having MOS transistors using the power supply core voltage to generate a temperature-dependent voltage that varies independently of power supply core voltage variation.