Abstract: A switching circuit includes a switch having first and second terminals coupled between a voltage supply and ground potential and having a control terminal coupled to receive a control signal indicative of the output voltage of an associated semiconductor circuit. The switch also includes an output terminal coupled to the well region within which is formed the associated semiconductor circuit. In preferred embodiments, the control signal transitions from a first state to a second state when the output voltage exceeds a predetermined potential. In response thereto, the switching circuit changes the well potential of the associated semiconductor circuit from a first voltage to ground potential, wherein the first voltage is greater than ground potential.

Abstract: A circuit for generating a boosted voltage includes a logic portion and a switching portion. The logic portion is coupled to receive a clock signal and, in response thereto, provides control signals to an associated switching circuit. During a first portion of the clock signal cycle, the switching circuit pulls an output terminal of the circuit to the supply voltage. During a second portion of the clock signal cycle, the switching circuit utilizes a bootstrap capacitor to boost the output terminal of the circuit to approximately twice the supply voltage, while isolating the output terminal from the supply voltage.

Abstract: A switching circuit includes a first switch connected between a first node and a first potential, a second switch connected between the first node and a second potential levels, a third switch connected between the first node and an output terminal, and a fourth switch connected between the output terminal and a third potential. A first control signal controls the conductivity of the first and second switches, a second control signal controls the conductivity of the third switch, and a logical combination the first and second control signals controls the conductivity of the fourth switch.

Abstract: A nonvolatile PMOS memory array includes a plurality of pages, where each column of a page includes two series-connected PMOS OR strings in parallel with a bit line. Each PMOS OR string includes a PMOS select transistor coupled between the bit line and two series connected PMOS floating gate memory cells. The PMOS floating gate memory cells are programmed via channel hot electron (CHE) injection and erased via electron tunneling. A soft-program mechanism is used to compensate for over-erasing of the memory cells. In some embodiments, the bit lines are segmented along page boundaries to increase speed.

Abstract: A memory array includes a predetermined number of rows of PMOS Flash memory cells formed in each of a plurality of n- well regions of a semiconductor substrate, where each of the n- well regions defines a page of the memory array. In some embodiments, a plurality of bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the bit lines. In other embodiments, a plurality of sub-bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the sub-bit lines, and groups of a predetermined number of the sub-bit lines are selectively coupled to associated ones of a plurality of bit lines via pass transistors.