Abstract: The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly comprised of look-up tables, multiplexers, and a latch, implement functions such as addition, subtraction, multiplication, and can perform as shift registers, finite state machines, multiplexers, accumulators, counters, multi-level random logic, and look-up tables, among other functions. Having two outputs, the embodiments of the logic unit can operate in split-mode and perform two separate logic and/or arithmetic functions at the same time. Clusters of the proposed logic units, which utilize local interconnections instead of traditional routing channels, add to efficiency, speed, and reduce required real estate.

Abstract: The embodiments of the present invention relate to the general area of Field Programmable Gate Arrays and, in particular, to Field Programmable Gate Arrays (“FPGAs”) comprising memory cells with both volatile and nonvolatile properties, and the control and management of each portion to overcome the disadvantages of each individual technology. Some of the advantages of combining the two properties in a single FPGA are power reduction, shorter power-on time, configuration flexibility, instant-on logic capability, cost savings in system components including nonvolatile instant-on devices, configuration memories, and standard CMOS process. Furthermore, to optimize these and other advantages of the proposed architecture, additional apparatus and methods are presented to individually and collectively manage and control different parts of such hybrid FPGAs.

Abstract: The embodiments of the present invention relate to the general area of Field Programmable Gate Arrays and, in particular, to Field Programmable Gate Arrays (“FPGAs”) comprising memory cells with both volatile and nonvolatile properties, and the control and management of each portion to overcome the disadvantages of each individual technology. Some of the advantages of combining the two properties in a single FPGA are power reduction, shorter power-on time, configuration flexibility, instant-on logic capability, cost savings in system components including nonvolatile instant-on devices, configuration memories, and standard CMOS process. Furthermore, to optimize these and other advantages of the proposed architecture, additional apparatus and methods are presented to individually and collectively manage and control different parts of such hybrid FPGAs.

Abstract: The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly comprised of look-up tables, multiplexers, and a latch, implement functions such as addition, subtraction, multiplication, and can perform as shift registers, finite state machines, multiplexers, accumulators, counters, multi-level random logic, and look-up tables, among other functions. Having two outputs, the embodiments of the logic unit can operate in split-mode and perform two separate logic and/or arithmetic functions at the same time. Clusters of the proposed logic units, which utilize local interconnections instead of traditional routing channels, add to efficiency, speed, and reduce required real estate.

Abstract: The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly comprised of look-up tables, multiplexers, and a latch, implement functions such as addition, subtraction, multiplication, and can perform as shift registers, finite state machines, multiplexers, accumulators, counters, multi-level random logic, and look-up tables, among other functions. Having two outputs, the embodiments of the logic unit can operate in split-mode and perform two separate logic and/or arithmetic functions at the same time. Clusters of the proposed logic units, which utilize local interconnections instead of traditional routing channels, add to efficiency, speed, and reduce required real estate.