Abstract: An interleaver for combining at least two incoming signals into an analog output signal includes at least a first signal path and a second signal path. Each signal path has: an input terminal, a first gain stage for multiplying a signal coming from the input terminal with a first gain (a) to obtain a first signal, a mixer and a second gain stage for multiplying a signal coming from the input terminal with a second gain (b) before or after mixing it with a clock signal to obtain a second signal, an adder for adding the first and second signal to obtain an output signal of the signal path wherein the first and second gain are different from zero. The interleaver comprises an adder for adding the output signals from the signal paths.

Abstract: A communication system includes a base station, at least one remote radio head, and at least one channel. The base station has at least two digital modulators adapted for modulating a first and a second incoming radio signal to obtain a first and a second quantized signal, a multiplexer for interleaving the quantized signals, and a transmitter adapted for transmitting the resulting quantized signal over the channel to the remote radio head. The remote radio head includes a receiver adapted for capturing the quantized signal, a clock extraction module adapted for converting the signal from the receiver into a clock signal, a demultiplexer for splitting the quantized signal using the clock signal to obtain at least two quantized signals, and a filter adapted for removing quantization noise from the quantized signal from the receiver or the demultiplexer.

Abstract: A filter includes cascaded building blocks, for filtering an incoming signal. Each building block has first and second delay elements. A first scaling device is between an input node of the first delay element and an output node of the second delay element, and a second scaling device is between an output node of the first delay element and an input node of the second delay element. The building block has a cross scaling device between the output nodes of the first delay element and of the second delay element, and/or between the input nodes of the first delay element and of the second delay element. The building block is configured such that, in operation, incoming signals at the input node and output node of the second delay element are summed together.

Abstract: An interleaver for combining at least two incoming signals into an analog output signal includes at least a first signal path and a second signal path. Each signal path has: an input terminal, a first gain stage for multiplying a signal coming from the input terminal with a first gain (a) to obtain a first signal, a mixer and a second gain stage for multiplying a signal coming from the input terminal with a second gain (b) before or after mixing it with a clock signal to obtain a second signal, an adder for adding the first and second signal to obtain an output signal of the signal path wherein the first and second gain are different from zero. The interleaver comprises an adder for adding the output signals from the signal paths.

Abstract: A communication system includes a base station, at least one remote radio head, and at least one channel. The base station has at least two digital modulators adapted for modulating a first and a second incoming radio signal to obtain a first and a second quantized signal, a multiplexer for interleaving the quantized signals, and a transmitter adapted for transmitting the resulting quantized signal over the channel to the remote radio head. The remote radio head includes a receiver adapted for capturing the quantized signal, a clock extraction module adapted for converting the signal from the receiver into a clock signal, a demultiplexer for splitting the quantized signal using the clock signal to obtain at least two quantized signals, and a filter adapted for removing quantization noise from the quantized signal from the receiver or the demultiplexer.

Abstract: A communication system is provided for transmitting a RF signal, which has a frequency band. The communication system comprises: a sigma delta modulator for modulating the RF signal into a broadband signal wherein the signal to noise ratio of the broadband signal is higher in the frequency band of the RF signal than outside the frequency band of the RF signal; an optical transmitter connected with the sigma delta modulator and with an optical fiber for transmitting the broadband signal over the optical fiber; a photo-detector configured for receiving the broadband signal from the optical fiber and converting it into an electrical signal; an output device and a matching circuit configured for power matching and/or noise matching of the photo-detector, at the frequency band of the RF signal, with the output device.

Abstract: A communication system is provided for transmitting a RF signal, which has a frequency band. The communication system comprises: a sigma delta modulator for modulating the RF signal into a broadband signal wherein the signal to noise ratio of the broadband signal is higher in the frequency band of the RF signal than outside the frequency band of the RF signal; an optical transmitter connected with the sigma delta modulator and with an optical fiber for transmitting the broadband signal over the optical fiber; a photo-detector configured for receiving the broadband signal from the optical fiber and converting it into an electrical signal; an output device and a matching circuit configured for power matching and/or noise matching of the photo-detector, at the frequency band of the RF signal, with the output device.

Abstract: Described herein is a feed forward equalizer that is configured to operate in a normal operational mode and in a test operational mode. The feed forward equalizer has an input port and an output port which are used for the normal operational mode. A test input port and a test output port are provided in the feed forward equalizer, and are used for the test operational mode. Buffers may be provided for matching the impedance of respective ones of the input, output, test input, and test output ports. The feed forward equalizer allows testing during development, and once mounted in an integrated circuit, without interfering with the normal operational mode.

Abstract: Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n?1) different reference values, and having N sets of (n?1) output terminals for outputting N sets of (n?1) output signals indicating whether the value of the multi-level signal is below or above the (n?1) reference values. The circuitry also includes N sets of (n?1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n?1) sample-and-hold circuits for generating at least one binary signal having a period N*T.

Abstract: Described herein is a multi-level to binary converter in which a cascade of differential limiting amplifiers are utilised for each signal path to provide both increased gain and increased bandwidth without having to trade one off against the other. Where the multi-level data is duobinary, cascaded amplifiers are coupled to a XOR logic gate. In each path, a copy of the duobinary signal is level shifted using an adjustable threshold before amplification in an amplifier. The shifted and amplified signal is then fed to another amplifier where it undergoes the same steps. The outputs from each path are fed to the XOR logic gate to generate the desired binary signal, corresponding to a decoded synchronized NRZ data stream. Such a multi-level to binary converter is capable of performing at data rates of 50 to 80 Gb/s and above, and can easily be integrated within a chip for high-speed electrical backplane communication, optical backplanes or optical fibre links.

Abstract: Described herein is a feed forward equalizer that is configured to operate in a normal operational mode and in a test operational mode. The feed forward equalizer has an input port and an output port which are used for the normal operational mode. A test input port and a test output port are provided in the feed forward equalizer, and are used for the test operational mode. Buffers may be provided for matching the impedance of respective ones of the input, output, test input, and test output ports. The feed forward equalizer allows testing during development, and once mounted in an integrated circuit, without interfering with the normal operational mode.

Abstract: A filter, comprising: two source-follower stages connected in series and in between input nodes and output nodes, wherein inner nodes connect the two stages; and a frequency dependent feedback circuit connected between the input and output nodes, wherein the filter comprises additional frequency dependent feedback circuits connected between input nodes and inner nodes and between output nodes and inner nodes, the additional frequency dependent feedback circuits comprising capacitors.

Abstract: Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n?1) different reference values, and having N sets of (n?1) output terminals for outputting N sets of (n?1) output signals indicating whether the value of the multi-level signal is below or above the (n?1) reference values. The circuitry also includes N sets of (n?1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n?1) sample-and-hold circuits for generating at least one binary signal having a period N*T.

Abstract: A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.

Abstract: A filter, comprising: two source-follower stages connected in series and in between input nodes and output nodes, wherein inner nodes connect the two stages; and a frequency dependent feedback circuit connected between the input and output nodes, wherein the filter comprises additional frequency dependent feedback circuits connected between input nodes and inner nodes and between output nodes and inner nodes, the additional frequency dependent feedback circuits comprising capacitors.

Abstract: An amplifier circuit is disclosed. In one embodiment, the amplifier circuit includes an input configured to receive an input signal. The amplifier circuit further includes an amplifier connected to the input that is configured to receive the input signal and generate a modulated input signal based on the input signal and one of a first amplification level and a second amplification level. The amplifier comprises a first transistor configured to receive the input signal and a second transistor connected in cascode with the first transistor. The amplifier circuit further includes a switching component configured to switch the amplifier between the first amplification level and the second amplification level. The amplifier circuit still further includes an output connected to the amplifier and configured to output the modulated input signal.

Abstract: A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.

Abstract: An amplifier circuit is disclosed. In one embodiment, the amplifier circuit includes an input configured to receive an input signal. The amplifier circuit further includes an amplifier connected to the input that is configured to receive the input signal and generate a modulated input signal based on the input signal and one of a first amplification level and a second amplification level. The amplifier comprises a first transistor configured to receive the input signal and a second transistor connected in cascode with the first transistor. The amplifier circuit further includes a switching component configured to switch the amplifier between the first amplification level and the second amplification level. The amplifier circuit still further includes an output connected to the amplifier and configured to output the modulated input signal.

Abstract: The present invention discloses an analogue-to-digital converter comprising at least two voltage comparator devices. Each of the voltage comparator devices comprises a differential structure of transistors and is arranged for being fed with a same input signal and for generating an own internal voltage reference by means of an imbalance in the differential structure, said two internal voltage references being different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of the input signal.