Patents by Inventor Guy Townsend Hutchison
Guy Townsend Hutchison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240039867Abstract: A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.Type: ApplicationFiled: October 10, 2023Publication date: February 1, 2024Inventors: Guy Townsend Hutchison, Sachin Ramesh Gandhi, Tsahi Daniel, Gerald Schmidt, Albert Fishman, Martin Leslie White, Zubin Shah
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Patent number: 11824796Abstract: A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.Type: GrantFiled: August 13, 2020Date of Patent: November 21, 2023Assignee: MARVELL ASIA PTE, LTD.Inventors: Guy Townsend Hutchison, Sachin Ramesh Gandhi, Tsahi Daniel, Gerald Schmidt, Albert Fishman, Martin Leslie White, Zubin Shah
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Publication number: 20200374240Abstract: A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.Type: ApplicationFiled: August 13, 2020Publication date: November 26, 2020Inventors: Guy Townsend Hutchison, Sachin Ramesh Gandhi, Tsahi Daniel, Gerald Schmidt, Albert Fishman, Martin Leslie White, Zubin Shah
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Patent number: 10785169Abstract: A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.Type: GrantFiled: October 18, 2017Date of Patent: September 22, 2020Assignee: MARVELL ASIA PTE, LTD.Inventors: Guy Townsend Hutchison, Sachin Ramesh Gandhi, Tsahi Daniel, Gerald Schmidt, Albert Fishman, Martin Leslie White, Zubin Shah
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Patent number: 10579573Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.Type: GrantFiled: May 2, 2018Date of Patent: March 3, 2020Assignee: Cavium, LLCInventors: Guy Townsend Hutchison, Harish Krishnamoorthy, Gerald Schmidt, Vishal Anand
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Patent number: 10078605Abstract: Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.Type: GrantFiled: October 22, 2014Date of Patent: September 18, 2018Assignee: Cavium, Inc.Inventors: Vishal Anand, Harish Krishnamoorthy, Guy Townsend Hutchison, Gerald Schmidt
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Publication number: 20180246836Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.Type: ApplicationFiled: May 2, 2018Publication date: August 30, 2018Inventors: Guy Townsend Hutchison, Harish Krishnamoorthy, Gerald Schmidt, Vishal Anand
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Patent number: 9990324Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.Type: GrantFiled: October 22, 2014Date of Patent: June 5, 2018Assignee: Cavium Inc.Inventors: Guy Townsend Hutchison, Harish Krishnamoorthy, Gerald Schmidt, Vishal Anand
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Publication number: 20180041450Abstract: A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.Type: ApplicationFiled: October 18, 2017Publication date: February 8, 2018Inventors: Guy Townsend Hutchison, Sachin Ramesh Gandhi, Tsahi Daniel, Gerald Schmidt, Albert Fishman, Martin Leslie White, Zubin Shah
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Patent number: 9825884Abstract: A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.Type: GrantFiled: March 10, 2016Date of Patent: November 21, 2017Assignee: Cavium, Inc.Inventors: Guy Townsend Hutchison, Sachin Gandhi, Tsahi Daniel, Gerald Schmidt, Albert Fishman, Martin Leslie White, Zubin Shah
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Patent number: 9542342Abstract: A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2n, where n is the number of bits in the source identifier.Type: GrantFiled: October 22, 2014Date of Patent: January 10, 2017Assignee: Cavium, Inc.Inventors: Vishal Anand, Harish Krishnamoorthy, Guy Townsend Hutchison
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Publication number: 20160197852Abstract: A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.Type: ApplicationFiled: March 10, 2016Publication date: July 7, 2016Inventors: Guy Townsend Hutchison, Sachin Gandhi, Tsahi Daniel, Gerald Schmidt, Albert Fishman, Martin Leslie White, Zubin Shah
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Publication number: 20160117282Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.Type: ApplicationFiled: October 22, 2014Publication date: April 28, 2016Inventors: Guy Townsend Hutchison, Harish Krishnamoorthy, Gerald Schmidt, Vishal Anand
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Publication number: 20160117271Abstract: A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2n, where n is the number of bits in the source identifier.Type: ApplicationFiled: October 22, 2014Publication date: April 28, 2016Inventors: Vishal Anand, Harish Krishnamoorthy, Guy Townsend Hutchison
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Publication number: 20160117273Abstract: Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.Type: ApplicationFiled: October 22, 2014Publication date: April 28, 2016Inventors: Vishal Anand, Harish Krishnamoorthy, Guy Townsend Hutchison, Gerald Schmidt
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Patent number: 7523251Abstract: A quaternary content-addressable memory includes multiple entries configured to match a lookup word, with each of these entries including multiple cells and with the lookup word including multiple lookup bits for matching corresponding cells of each of the entries. Each of the cells is individually configurable to be in one of multiple states identified by two bits, with these states including a first matching state for matching a value of a corresponding bit of the lookup word with the value having a first matching value, a second matching state for matching the value of the corresponding bit having a second matching value, a wildcard state for matching the value of the corresponding bit having either the first or the second matching value, and an ignore state for indicating to ignore the cell in determining whether or not the entry to which the cell belongs matches the lookup word.Type: GrantFiled: January 18, 2005Date of Patent: April 21, 2009Assignee: Cisco Technology, Inc.Inventors: Awais Bin Nemat, Sachin Ramesh Gandhi, Guy Townsend Hutchison, Ben Xin Chen
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Patent number: 6629118Abstract: A zero result detector for detecting a zero result in the sum of a first operand A, a second operand B and a carry bit Cin operates by calculating {overscore (A)} and {overscore (A)}+1 and then comparing one of these with B (Cin=O, {overscore (A)}; Cin=1, {overscore (A)}+1) in dependence upon Cin. If the comparison shows equality, then the zero detect result Z is true.Type: GrantFiled: December 7, 1999Date of Patent: September 30, 2003Assignee: ARM LimitedInventors: Guy Townsend Hutchison, David William Steer