Abstract: A driver for a circuit with a capacitive load is configured for coupling to a voltage source which provides a DC input voltage, and is configured to generate an output voltage at an output. The driver includes a bidirectional synchronous power converter with a first switch, a second switch, and an inductive device connected to the first and/or second switch. A controller is configured to control the first switch and the second switch. The bidirectional synchronous power converter generates a switching voltage from the input voltage at a switching node and generates the output voltage having an analog voltage waveform with a peak amplitude of at least twice the input voltage.

Abstract: A driver for a circuit with a capacitive load is configured for coupling to a voltage source which provides a DC input voltage, and is configured to generate an output voltage at an output. The driver includes a bidirectional synchronous power converter with a first switch, a second switch, and an inductive device connected to the first and/or second switch. A controller is configured to control the first switch and the second switch. The bidirectional synchronous power converter generates a switching voltage from the input voltage at a switching node and generates the output voltage having an analog voltage waveform with a peak amplitude of at least twice the input voltage.

Abstract: Methods and apparatus for parallel processing are provided. A multicore processor is described. The multicore processor may include a distributed memory unit with memory nodes coupled to the processor's cores. The cores may be configured to execute parallel threads, and at least one of the threads may be data-dependent on at least one of the other threads. The distributed memory unit may be configured to proactively send shared memory data from a thread that produces the shared memory data to one or more of the threads.

Abstract: A driver for a circuit with a capacitive load is configured for coupling to a voltage source which provides a DC input voltage, and is configured to generate an output voltage at an output. The driver includes a bidirectional synchronous power converter with a first switch, a second switch, and an inductive device connected to the first and/or second switch. A controller is configured to control the first switch and the second switch. The bidirectional synchronous power converter generates a switching voltage from the input voltage at a switching node and generates the output voltage having an analog voltage waveform with a peak amplitude of at least twice the input voltage. The bidirectional synchronous power converter includes a boost-buck converter configured to generate the analog voltage waveform from the input voltage by transferring increments of energy to the capacitive load in a forward-boost mode and from the load in a reverse-buck mode.

Abstract: A driver for a circuit with a capacitive load is configured for coupling to a voltage source which provides a DC input voltage, and is configured to generate an output voltage at an output. The driver includes a bidirectional synchronous power converter with a first switch, a second switch, and an inductive device connected to the first and/or second switch. A controller is configured to control the first switch and the second switch. The bidirectional synchronous power converter generates a switching voltage from the input voltage at a switching node and generates the output voltage having an analog voltage waveform with a peak amplitude of at least twice the input voltage. The bidirectional synchronous power converter includes a boost-buck converter configured to generate the analog voltage waveform from the input voltage by transferring increments of energy to the capacitive load in a forward-boost mode and from the load in a reverse-buck mode.

Abstract: A single ended n-bit hybrid digital-to-analog converter is configured to receive as an input an analog signal and produce an n-bit digital output. The converter includes a split main sub-digital-to-analog converter capacitor array, a most significant bit capacitor array, and a main capacitor array. A coupling capacitor couples the main array to the split main sub-digital-to-analog convert.

Abstract: A single die driver integrated circuit is coupled to an input portion having a single inductor receiving a low voltage source and configured to drive a capacitive load with an output voltage. The driver includes a bidirectional synchronous power converter stage configured to generate a switching voltage from the input portion at a switching node and to generate a high voltage waveform from the low-voltage source. An embedded controller is configured to control a switch of the power converter stage.

Abstract: A single ended n-bit hybrid digital-to-analog converter is configured to receive as an input an analog signal and produce an n-bit digital output. The converter includes a split main sub-digital-to-analog converter capacitor array, a most significant bit capacitor array, and a main capacitor array. A coupling capacitor couples the main array to the split main sub-digital-to-analog convert.

Abstract: A single die driver integrated circuit is coupled to an input portion having a single inductor receiving a low voltage source and configured to drive a capacitive load with an output voltage. The driver includes a bidirectional synchronous power converter stage configured to generate a switching voltage from the input portion at a switching node and to generate a high voltage waveform from the low-voltage source. An embedded controller is configured to control a switch of the power converter stage.

Abstract: A switched capacitor converter and a method for configuring the switched capacitor converter are disclosed. The switched capacitor converter includes a capacitance resource with a cathode and an anode and a switching matrix with a first terminal, a second terminal, a third terminal, and at least one switch configured to switch among two or more connections selected from the group consisting of a connection of the first terminal to the anode and the second terminal to the cathode and a connection of the second terminal to the anode and the third terminal to the cathode.

Abstract: A device and method for hybrid feedback control of a switch-capacitor multi-unit voltage regulator are presented. A multi-unit switched-capacitor (SC) core includes a plurality of SC converter units, each unit with a capacitor and a plurality of switches controllable by a plurality of switching signals. Power switch drivers provide a switching signal to each SC converter unit. A secondary proactive loop circuit includes a feedback control circuit configured to control one or more of the plurality of switches. A comparator is configured to compare the regulator output voltage with a reference voltage and provide a comparator trigger signal. Ripple reduction logic is configured to receive the comparator trigger signal and provide an SC unit allocation signal. A multiplexer is configured to receive a first clock signal, a second clock signal, and the SC unit allocation signal and provide a signal to the power switch drivers.

Abstract: A switched capacitor converter and a method for configuring the switched capacitor converter are disclosed. The switched capacitor converter includes a capacitance resource with a cathode and an anode and a switching matrix with a first terminal, a second terminal, a third terminal, and at least one switch configured to switch among two or more connections selected from the group consisting of a connection of the first terminal to the anode and the second terminal to the cathode and a connection of the second terminal to the anode and the third terminal to the cathode.

Abstract: A device and method for hybrid feedback control of a switch-capacitor multi-unit voltage regulator are presented. A multi-unit switched-capacitor (SC) core includes a plurality of SC converter units, each unit with a capacitor and a plurality of switches controllable by a plurality of switching signals. Power switch drivers provide a switching signal to each SC converter unit. A secondary proactive loop circuit includes a feedback control circuit configured to control one or more of the plurality of switches. A comparator is configured to compare the regulator output voltage with a reference voltage and provide a comparator trigger signal. Ripple reduction logic is configured to receive the comparator trigger signal and provide an SC unit allocation signal. A multiplexer is configured to receive a first clock signal, a second clock signal, and the SC unit allocation signal and provide a signal to the power switch drivers.

Abstract: Methods and apparatus for parallel processing are provided. A multicore processor is described. The multicore processor may include a distributed memory unit with memory nodes coupled to the processor's cores. The cores may be configured to execute parallel threads, and at least one of the threads may be data-dependent on at least one of the other threads. The distributed memory unit may be configured to proactively send shared memory data from a thread that produces the shared memory data to one or more of the threads.

Abstract: A circuit for driving a plurality of capacitive actuators, the circuit having a low-voltage side, a high voltage side and a flyback transformer between the two. The low-voltage side comprises first and second pairs of low-side switches connected in series across an input voltage. The flyback transformer has a primary winding connected to the two pairs of switches. The high-voltage side has a pair of switches connected between the secondary winding of the flyback transformer and a ground and a plurality of capacitive loads and bidirectional switches to connect the loads to the secondary winding of the flyback transformer and a ground.

Abstract: In a preferred embodiment, the present invention is a system for avoiding voltage emergencies. The system comprises a microprocessor, an actuator for throttling the microprocessor, a voltage emergency detector and a voltage emergency predictor. The voltage emergency detector may comprise, for example, a checkpoint recovery mechanism or a sensor. The voltage emergency predictor of a preferred embodiment comprises means for tracking control flow instructions and microarchitectural events, means for storing voltage emergency signatures that cause voltage emergencies, means for comparing current control flow and microarchitectural events with stored voltage emergency signatures to predict voltage emergencies, and means for actuating said actuator to throttle said microprocessor to avoid predicted voltage emergencies.

Abstract: A circuit for driving a plurality of capacitive actuators, the circuit having a low-voltage side, a high voltage side and a flyback transformer between the two. The low-voltage side comprises first and second pairs of low-side switches connected in series across an input voltage. The flyback transformer has a primary winding connected to the two pairs of switches. The high-voltage side has a pair of switches connected between the secondary winding of the flyback transformer and a ground and a plurality of capacitive loads and bidirectional switches to connect the loads to the secondary winding of the flyback transformer and a ground.

Abstract: The present invention reveals a semiconductor chip structure and its application circuit network, wherein the switching voltage regulator or converter is integrated with a semiconductor chip by chip fabrication methods, so that the semiconductor chip has the ability to regulate voltage within a specific voltage range. Therefore, when many electrical devices of different working voltages are placed on a Printed Circuit Board (PCB), only a certain number of semiconductor chips need to be constructed. Originally, in order to account for the different demands in voltage, power supply units of different output voltages, or a variety of voltage regulators need to be added. However, using the built-in voltage regulator or converter, the voltage range can be immediately adjusted to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices.

Abstract: In a preferred embodiment, the present invention is a system for avoiding voltage emergencies. The system comprises a microprocessor, an actuator for throttling the microprocessor, a voltage emergency detector and a voltage emergency predictor. The voltage emergency detector may comprise, for example, a checkpoint recovery mechanism or a sensor. The voltage emergency predictor of a preferred embodiment comprises means for tracking control flow instructions and microarchitectural events, means for storing voltage emergency signatures that cause voltage emergencies, means for comparing current control flow and microarchitectural events with stored voltage emergency signatures to predict voltage emergencies, and means for actuating said actuator to throttle said microprocessor to avoid predicted voltage emergencies.

Abstract: A circuit having dynamically controllable power. The circuit comprises a plurality of pipelined stages, each of the pipelined stages comprising two clocking domains, a plurality of switching circuits, each switching circuit being connected to one of the pipelined stages, first and second power sources connected to each of the plurality of pipelined stages through the switching circuits, the first power source supplying a first voltage and the second power source supplying a second voltage, wherein the first and second power sources each may be applied to a pipelined stage independently of other pipelined stages, first and second complementary clocks, and a plurality of latches connected to the first and second complementary clocks and to the plurality of pipelined stages for proving latch-based clocking to control the first and second clocking domains and to enable time-borrowing across the plurality of switching circuits.