Patents by Inventor Guyoung Cho
Guyoung Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230317728Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.Type: ApplicationFiled: May 23, 2023Publication date: October 5, 2023Inventors: Guyoung CHO, Subin SHIN, DONGHYUN ROH, Byung-Suk JUNG, SANGJIN HYUN
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Patent number: 11676967Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.Type: GrantFiled: May 20, 2022Date of Patent: June 13, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Guyoung Cho, Subin Shin, Donghyun Roh, Byung-Suk Jung, Sangjin Hyun
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Publication number: 20220278101Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.Type: ApplicationFiled: May 20, 2022Publication date: September 1, 2022Inventors: Guyoung CHO, Subin SHIN, DONGHYUN ROH, Byung-Suk JUNG, SANGJIN HYUN
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Patent number: 11342328Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.Type: GrantFiled: July 30, 2020Date of Patent: May 24, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Guyoung Cho, Subin Shin, Donghyun Roh, Byung-Suk Jung, Sangjin Hyun
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Patent number: 10840331Abstract: A semiconductor device includes active patterns protruding from a substrate and an insulation structure surrounding lower portions of the active patterns. The insulation structure includes an insulation layer conforming to a top surface of the substrate and to sidewalls of the active patterns and a buried insulation pattern on the insulation layer.Type: GrantFiled: April 17, 2018Date of Patent: November 17, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Guyoung Cho, Dae-Young Kwak, Shinhye Kim, Koungmin Ryu, Sangjin Hyun
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Publication number: 20200357800Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.Type: ApplicationFiled: July 30, 2020Publication date: November 12, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Guyoung CHO, Subin SHIN, DONGHYUN ROH, Byung-Suk JUNG, SANGJIN HYUN
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Patent number: 10784262Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.Type: GrantFiled: January 12, 2019Date of Patent: September 22, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Guyoung Cho, Subin Shin, Donghyun Roh, Byung-Suk Jung, Sangjin Hyun
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Publication number: 20200006342Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.Type: ApplicationFiled: February 12, 2019Publication date: January 2, 2020Inventors: Guyoung CHO, Subin SHIN, DONGHYUN ROH, Byung-Suk JUNG, SANGJIN HYUN
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Publication number: 20190058035Abstract: A semiconductor device includes active patterns protruding from a substrate and an insulation structure surrounding lower portions of the active patterns. The insulation structure includes an insulation layer conforming to a top surface of the substrate and to sidewalls of the active patterns and a buried insulation pattern on the insulation layer.Type: ApplicationFiled: April 17, 2018Publication date: February 21, 2019Inventors: Guyoung Cho, Dae-Young Kwak, Shinhye Kim, Koungmin Ryu, Sangjin Hyun