Patents by Inventor Gwan Park

Gwan Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250058330
    Abstract: Disclosed are an electrostatic precipitator system and method. The disclosed electrostatic precipitator system includes: an electrostatic precipitator; a main hopper which is disposed below the electrostatic precipitator so as to be in fluid communication with the electrostatic precipitator; a plurality of sub-hoppers disposed below the main hopper so as to be in fluid communication with the main hopper; a vertical duct disposed below each sub-hopper so as to be in fluid communication with each sub-hopper; and a water tank disposed below the vertical duct so as to be in fluid communication with the vertical duct.
    Type: Application
    Filed: November 8, 2022
    Publication date: February 20, 2025
    Applicant: Samsung E&A Co., Ltd.
    Inventors: Chae Gwan PARK, Joeng Min OH, Tae Jin PARK, Jun Ho SEO, Yong Jung KIM
  • Patent number: 12225741
    Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: February 11, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-chan Suh, Gi-gwan Park, Dong-woo Kim, Dong-suk Shin
  • Patent number: 12211846
    Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.
    Type: Grant
    Filed: January 18, 2024
    Date of Patent: January 28, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Soo Kim, Gi Gwan Park, Jung Hun Choi, Koung Min Ryu, Sun Jung Lee
  • Patent number: 12203650
    Abstract: A waste heat recovery system and method are disclosed. The waste heat recovery system disclosed herein comprises: a waste heat recovery boiler; a waste heat supply member configured to supply waste heat to the waste heat recovery boiler; and a water tank configured to fluidly communicate with the waste heat supply member.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: January 21, 2025
    Assignee: SAMSUNG E&A CO., LTD.
    Inventors: Chae Gwan Park, Joeng Min Oh, Tae Jin Park, Jun Ho Seo, Yong Jung Kim
  • Publication number: 20250020451
    Abstract: An apparatus for continuously measuring the thickness of a thin material includes a main frame configured by upper and lower frames provided in a direction crossing with a movement direction of a thin material and a vertical frame which connects the upper and lower frames, upper and lower sliders moved by sliding along guide grooves formed in the upper and lower frames; an upper confocal sensor radiating light toward the thin material, and a lower confocal sensor radiating light toward the thin material, wherein the upper and lower confocal sensors are disposed on the same axis, and height measurement is performed by receiving light only at a moment when a focus coincides at a measurement position, and wherein the upper confocal sensor and the upper slider and the lower confocal sensor and the lower slider are synchronously controlled, and are controlled in conjunction with movement of the thin material.
    Type: Application
    Filed: August 7, 2023
    Publication date: January 16, 2025
    Applicant: KOREA ELECTROTECHNOLOGY RESEARCH INSTITUTE
    Inventors: In Sung PARK, Gwan Tae KIM, Ho Sup KIM, Hong Soo HA
  • Publication number: 20240418360
    Abstract: A waste heat recovery system and method are disclosed. The waste heat recovery system disclosed herein comprises: a waste heat recovery boiler; a waste heat supply member configured to supply waste heat to the waste heat recovery boiler; and a water tank configured to fluidly communicate with the waste heat supply member.
    Type: Application
    Filed: November 9, 2022
    Publication date: December 19, 2024
    Applicant: Samsung E&A Co., Ltd.
    Inventors: Chae Gwan PARK, Joeng Min OH, Tae Jin PARK, Jun Ho SEO, Yong Jung KIM
  • Patent number: 12078506
    Abstract: The region segmentation apparatus and method for map decomposition of a robot according to the exemplary embodiment of the present disclosure segment the grid map into a plurality of regions in consideration of the graphic characteristic of the space and obstacles disposed in the space.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: September 3, 2024
    Assignees: Yujin Robot Co., Ltd., Miele & Cie. KG
    Inventors: Seong Ju Park, Chang Soo Kim, Ji Gwan Park, Jin Baek Kim, Dong Hyeon Seo
  • Publication number: 20240290888
    Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.
    Type: Application
    Filed: May 10, 2024
    Publication date: August 29, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hoon LEE, Gi-gwan PARK, Tae-young KIM
  • Publication number: 20240224487
    Abstract: A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.
    Type: Application
    Filed: March 13, 2024
    Publication date: July 4, 2024
    Inventors: KI-IL KIM, Jung-gun YOU, Gi-gwan PARK
  • Patent number: 12015086
    Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: June 18, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hoon Lee, Gi-gwan Park, Tae-young Kim
  • Publication number: 20240150766
    Abstract: The present invention relates to a multi-conjugate of small interfering RNA (siRNA) and a preparing method of the same, more precisely a multi-conjugate of siRNA prepared by direct binding of double stranded sense/antisense siRNA monomers or indirect covalent bonding mediated by a cross-linking agent or a polymer, and a preparing method of the same. The preparing method of a siRNA multi-conjugate of the present invention is characterized by simple and efficient reaction and thereby the prepared siRNA multi-conjugate of the present invention has high molecular weight multiple times the conventional siRNA, so that it has high negative charge density, suggesting that it has excellent ionic interaction with a cationic gene carrier and high gene delivery efficiency.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 9, 2024
    Inventors: Tae Gwan Park, Hye Jung Mok, Soo Hyeon Lee
  • Publication number: 20240153948
    Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung Soo KIM, Gi Gwan PARK, Jung Hun CHOI, Koung Min RYU, Sun Jung LEE
  • Patent number: 11956937
    Abstract: A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Il Kim, Jung-Gun You, Gi-Gwan Park
  • Patent number: 11908858
    Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Soo Kim, Gi Gwan Park, Jung Hun Choi, Koung Min Ryu, Sun Jung Lee
  • Publication number: 20240038841
    Abstract: There is provided a semiconductor device capable of capable of improving element performance and reliability. A semiconductor device includes a lower conductive pattern disposed on a substrate, an upper conductive pattern disposed on the lower conductive pattern, and a first plug pattern disposed between the lower conductive pattern and the upper conductive pattern and connected to the lower conductive pattern and the upper conductive pattern. The first plug pattern includes a first barrier pattern that defines a first plug recess and a first plug metal pattern that fills the first plug recess, and the first plug metal pattern includes a first molybdenum pattern and a first tungsten pattern disposed on the first molybdenum pattern.
    Type: Application
    Filed: March 22, 2023
    Publication date: February 1, 2024
    Inventors: Gi Gwan PARK, Jung Gun You, Sun Jung Lee
  • Patent number: 11859184
    Abstract: The present invention relates to a multi-conjugate of small interfering RNA (siRNA) and a preparing method of the same, more precisely a multi-conjugate of siRNA prepared by direct binding of double stranded sense/antisense siRNA monomers or indirect covalent bonding mediated by a cross-linking agent or a polymer, and a preparing method of the same. The preparing method of a siRNA multi-conjugate of the present invention is characterized by simple and efficient reaction and thereby the prepared siRNA multi-conjugate of the present invention has high molecular weight multiple times the conventional siRNA, so that it has high negative charge density, suggesting that it has excellent ionic interaction with a cationic gene carrier and high gene delivery efficiency.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: January 2, 2024
    Assignee: Kip Co., Ltd.
    Inventors: Tae Gwan Park, Hye Jung Mok, Soo Hyeon Lee
  • Publication number: 20230343787
    Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: Dong-chan SUH, Gi-gwan PARK, Dong-woo KIM, Dong-suk SHIN
  • Patent number: 11728345
    Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-chan Suh, Gi-gwan Park, Dong-woo Kim, Dong-suk Shin
  • Publication number: 20230219251
    Abstract: The present invention relates to a multifunctional wood preservative composition containing a compound prepared by reaction of hydrazine hydrate and boric acid and to a method for wood preservation treatment using the same. The wood preservative composition of the present invention can not only impart flame retardant, insect-repellent, rot-resistant, insect-repellent, and rust-proof effects to wood, such as various wooden structures including wooden cultural assets, but also causes no whitening and makes relatively fewer color changes for dancheong. Furthermore, the wood preservative composition of the present invention is provided as a one-component type liquid and thus can save time and costs for wood treatment and is convenient to use.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 13, 2023
    Inventors: Jinqyu KIM, Jae-Gwan PARK, Kyung Tae HONG, Soo Chang SONG, Jin Gu KANG
  • Publication number: 20230070118
    Abstract: The present invention relates to a multi-conjugate of small interfering RNA (siRNA) and a preparing method of the same, more precisely a multi-conjugate of siRNA prepared by direct binding of double stranded sense/antisense siRNA monomers or indirect covalent bonding mediated by a cross-linking agent or a polymer, and a preparing method of the same. The preparing method of a siRNA multi-conjugate of the present invention is characterized by simple and efficient reaction and thereby the prepared siRNA multi-conjugate of the present invention has high molecular weight multiple times the conventional siRNA, so that it has high negative charge density, suggesting that it has excellent ionic interaction with a cationic gene carrier and high gene delivery efficiency.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 9, 2023
    Inventors: Tae Gwan Park, Hye Jung Mok, Soo Hyeon Lee