Abstract: A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

Abstract: There is provided a semiconductor device capable of capable of improving element performance and reliability. A semiconductor device includes a lower conductive pattern disposed on a substrate, an upper conductive pattern disposed on the lower conductive pattern, and a first plug pattern disposed between the lower conductive pattern and the upper conductive pattern and connected to the lower conductive pattern and the upper conductive pattern. The first plug pattern includes a first barrier pattern that defines a first plug recess and a first plug metal pattern that fills the first plug recess, and the first plug metal pattern includes a first molybdenum pattern and a first tungsten pattern disposed on the first molybdenum pattern.

Abstract: The present invention relates to a multi-conjugate of small interfering RNA (siRNA) and a preparing method of the same, more precisely a multi-conjugate of siRNA prepared by direct binding of double stranded sense/antisense siRNA monomers or indirect covalent bonding mediated by a cross-linking agent or a polymer, and a preparing method of the same. The preparing method of a siRNA multi-conjugate of the present invention is characterized by simple and efficient reaction and thereby the prepared siRNA multi-conjugate of the present invention has high molecular weight multiple times the conventional siRNA, so that it has high negative charge density, suggesting that it has excellent ionic interaction with a cationic gene carrier and high gene delivery efficiency.

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

Abstract: The present invention relates to a multifunctional wood preservative composition containing a compound prepared by reaction of hydrazine hydrate and boric acid and to a method for wood preservation treatment using the same. The wood preservative composition of the present invention can not only impart flame retardant, insect-repellent, rot-resistant, insect-repellent, and rust-proof effects to wood, such as various wooden structures including wooden cultural assets, but also causes no whitening and makes relatively fewer color changes for dancheong. Furthermore, the wood preservative composition of the present invention is provided as a one-component type liquid and thus can save time and costs for wood treatment and is convenient to use.

Abstract: The present invention relates to a multi-conjugate of small interfering RNA (siRNA) and a preparing method of the same, more precisely a multi-conjugate of siRNA prepared by direct binding of double stranded sense/antisense siRNA monomers or indirect covalent bonding mediated by a cross-linking agent or a polymer, and a preparing method of the same. The preparing method of a siRNA multi-conjugate of the present invention is characterized by simple and efficient reaction and thereby the prepared siRNA multi-conjugate of the present invention has high molecular weight multiple times the conventional siRNA, so that it has high negative charge density, suggesting that it has excellent ionic interaction with a cationic gene carrier and high gene delivery efficiency.

Abstract: A memory device comprises: a page buffer including a first and second latch, a control circuit configured to perform reading data of a word line and storing the data in the first latch, perform discharging the word line, perform moving the data of the first latch to the second latch, and perform outputting the data of the second latch to an exterior, and a control logic configured to control the control circuit such that an execution section of the discharge and moving for a first word line at least partially overlap each other when a second or third cache read command is inputted in a section in which the storage or discharge for the first word line is performed in response to a first cache read command for the first word line.

Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.

Abstract: A memory device comprises: a page buffer including a first and second latch, a control circuit configured to perform reading data of a word line and storing the data in the first latch, perform discharging the word line, perform moving the data of the first latch to the second latch, and perform outputting the data of the second latch to an exterior, and a control logic configured to control the control circuit such that an execution section of the discharge and moving for a first word line at least partially overlap each other when a second or third cache read command is inputted in a section in which the storage or discharge for the first word line is performed in response to a first cache read command for the first word line.

Abstract: A memory device may include a first sub-block and a second sub-block each including a plurality of select transistors and a plurality of memory cells, a peripheral circuit performing a read operation on data stored in the first sub-block, and a control logic controlling the peripheral circuit to turn on the plurality of select transistors included in each of the first and second sub-blocks and apply a read voltage to a selected word line among a plurality of word lines.

Abstract: The region segmentation apparatus and method for map decomposition of a robot according to the exemplary embodiment of the present disclosure segment the grid map into a plurality of regions in consideration of the graphic characteristic of the space and obstacles disposed in the space.

Abstract: A map noise reduction apparatus and method of a robot according to the exemplary embodiment of the present disclosure reduce a noise such as an outer noise and an inner nose which may be caused due to a sensor characteristic and an environmental factor while generating a grid map and simplify a contour of the grid map to provide a neater and clear grid map.

Abstract: A semiconductor device including a substrate includes a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first lower TiN layer on and in contact with the first gate insulating layer, a first etch-stop layer on the first lower TiN layer and a first upper gate electrode on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second lower TiN layer on and in contact with the second gate insulating layer, a second etch-stop layer on the second lower TiN layer and a second upper gate electrode on the second etch-stop layer. A thickness of the first lower TiN layer is less than a thickness of the second lower TiN layer.

Abstract: Methods for fabricating semiconductor devices include forming a fin-type pattern protruding on a substrate, forming a gate electrode intersecting the fin-type pattern, forming a first recess adjacent to the gate electrode and within the fin-type pattern by using dry etching, forming a second recess by treating a surface of the first recess with a surface treatment process including a deposit process and an etch process, and forming an epitaxial pattern in the second recess.

Abstract: A memory device includes a plurality of memory cell arrays each configured to include a plurality of memory cells, a plurality of peripheral circuits each configured to perform operations on the plurality of memory cell arrays, a plurality of control logics configured to control the plurality of peripheral circuits, and a control logic selector configured to activate at least one control logic among the plurality of control logics according to a type of a command received from the memory controller.

Abstract: A semiconductor device including a substrate with a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first etch-stop layer, and a first work function layer on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second etch-stop layer, and a second work function layer on the second etch-stop layer. At least one of the first and second work function layers is chamfered.

Abstract: A memory device may include a first sub-block and a second sub-block each including a plurality of select transistors and a plurality of memory cells, a peripheral circuit performing a read operation on data stored in the first sub-block, and a control logic controlling the peripheral circuit to turn on the plurality of select transistors included in each of the first and second sub-blocks and apply a read voltage to a selected word line among a plurality of word lines.

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.