Patents by Inventor Gwan S. Choi

Gwan S. Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LOW DENSITY PARITY CHECK DECODER
    Publication number: 20230336189
    Abstract: A method and system for decoding low density parity check (LDPC) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Applicant: The Texas A&M University System
    Inventors: Kiran Kumar GUNNAM, Gwan S. CHOI
  • Low density parity check decoder
    Patent number: 11728828
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: August 15, 2023
    Assignee: The Texas A&M University System
    Inventors: Kiran Kumar Gunnam, Gwan S. Choi
  • LOW DENSITY PARITY CHECK DECODER
    Publication number: 20220294472
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.
    Type: Application
    Filed: May 13, 2022
    Publication date: September 15, 2022
    Applicant: The Texas A&M University System
    Inventors: Kiran Kumar GUNNAM, Gwan S. CHOI
  • Low density parity check decoder
    Patent number: 11368168
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: June 21, 2022
    Assignee: The Texas A&M University System
    Inventors: Kiran Kumar Gunnam, Gwan S. Choi
  • Low density parity check decoder
    Patent number: 10951235
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: March 16, 2021
    Assignee: The Texas A&M University System
    Inventors: Kiran Kumar Gunnam, Gwan S. Choi
  • LOW DENSITY PARITY CHECK DECODER
    Publication number: 20210067175
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.
    Type: Application
    Filed: October 29, 2020
    Publication date: March 4, 2021
    Applicant: The Texas A&M University System
    Inventors: Kiran Kumar GUNNAM, Gwan S. CHOI
  • Low density parity check decoder
    Patent number: 10615823
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 7, 2020
    Assignee: The Texas A&M University System
    Inventors: Kiran Kumar Gunnam, Gwan S. Choi
  • Low Density Parity Check Decoder
    Publication number: 20190052288
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Applicant: The Texas A&M University System
    Inventors: Kiran Kumar GUNNAM, Gwan S. CHOI
  • Low density parity check decoder
    Patent number: 10141950
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: November 27, 2018
    Assignee: THE TEXAS A&M UNIVERSITY SYSTEM
    Inventors: Kiran Kumar Gunnam, Gwan S. Choi
  • LOW DENSITY PARITY CHECK DECODER
    Publication number: 20170093429
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.
    Type: Application
    Filed: December 9, 2016
    Publication date: March 30, 2017
    Applicant: The Texas A&M University System
    Inventors: Kiran Kumar GUNNAM, Gwan S. CHOI
  • LOW DENSITY PARITY CHECK DECODER
    Publication number: 20150311917
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry.
    Type: Application
    Filed: July 7, 2015
    Publication date: October 29, 2015
    Applicant: The Texas A&M University System
    Inventors: Kiran Kumar GUNNAM, Gwan S. CHOI
  • Low density parity check decoder
    Patent number: 9112530
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 18, 2015
    Assignee: THE TEXAS A&M UNIVERSITY SYSTEM
    Inventors: Kiran Kumar Gunnam, Gwan S. Choi
  • LOW DENSITY PARITY CHECK DECODER
    Publication number: 20140181612
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.
    Type: Application
    Filed: December 27, 2013
    Publication date: June 26, 2014
    Applicant: TEXAS A&M UNIVERSITY SYSTEM
    Inventors: Kiran Kumar GUNNAM, Gwan S. CHOI
  • Low density parity check decoder for regular LDPC codes
    Patent number: 8656250
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: February 18, 2014
    Assignee: Texas A&M University System
    Inventors: Kiran Kumar Gunnam, Gwan S. Choi
  • Low density parity check decoder for irregular LDPC codes
    Patent number: 8555140
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: October 8, 2013
    Assignee: The Texas A&M University System
    Inventors: Kiran Kumar Gunnam, Gwan S. Choi
  • Low density parity check decoder for irregular LDPC codes
    Patent number: 8418023
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: April 9, 2013
    Assignee: The Texas A&M University System
    Inventors: Kiran K. Gunnam, Gwan S. Choi
  • Low density parity check decoder for regular LDPC codes
    Patent number: 8359522
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: January 22, 2013
    Assignee: Texas A&M University System
    Inventors: Kiran K. Gunnam, Gwan S. Choi
  • LOW DENSITY PARITY CHECK DECODER FOR IRREGULAR LDPC CODES
    Publication number: 20080301521
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order.
    Type: Application
    Filed: May 1, 2008
    Publication date: December 4, 2008
    Applicant: TEXAS A&M UNIVERSITY SYSTEM
    Inventors: Kiran K. GUNNAM, Gwan S. CHOI
  • LOW DENSITY PARITY CHECK DECODER FOR REGULAR LDPC CODES
    Publication number: 20080276156
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.
    Type: Application
    Filed: May 1, 2008
    Publication date: November 6, 2008
    Applicant: TEXAS A&M UNIVERSITY SYSTEM
    Inventors: Kiran K. GUNNAM, Gwan S. CHOI