Patents by Inventor Gwang Jae JEON
Gwang Jae JEON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11715645Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: GrantFiled: March 28, 2022Date of Patent: August 1, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Park, Jin-Woo Park, Seok Hyun Lee, Jae Gwon Jang, Gwang Jae Jeon
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Publication number: 20220262696Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.Type: ApplicationFiled: May 3, 2022Publication date: August 18, 2022Inventors: Jung-Ho PARK, Jin-Woo PARK, Jae Gwon JANG, Gwang Jae JEON
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Publication number: 20220216068Abstract: A method for fabricating a semiconductor package, the method including: forming a. release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: ApplicationFiled: March 28, 2022Publication date: July 7, 2022Inventors: Jung-Ho PARK, Jin-Woo PARK, Seok Hyun LEE, Jae Gwon JANG, Gwang Jae JEON
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Patent number: 11373980Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.Type: GrantFiled: January 16, 2020Date of Patent: June 28, 2022Assignee: Samsung Electronics Co, Ltd.Inventors: Jong Youn Kim, Dong Kyu Kim, Jin-Woo Park, Min Jun Bae, Gwang Jae Jeon
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Patent number: 11328970Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.Type: GrantFiled: May 5, 2020Date of Patent: May 10, 2022Inventors: Jung-Ho Park, Jin-Woo Park, Jae Gwon Jang, Gwang Jae Jeon
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Patent number: 11322368Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: GrantFiled: September 29, 2020Date of Patent: May 3, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Park, Jin-Woo Park, Seok Hyun Lee, Jae Gwon Jang, Gwang Jae Jeon
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Publication number: 20210257223Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: ApplicationFiled: September 29, 2020Publication date: August 19, 2021Inventors: Jung-Ho PARK, Jin-Woo PARK, Seok Hyun LEE, Jae Gwon JANG, Gwang Jae JEON
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Publication number: 20210066149Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.Type: ApplicationFiled: May 5, 2020Publication date: March 4, 2021Inventors: Jung-Ho PARK, Jin-Woo PARK, Jae Gwon JANG, Gwang Jae JEON
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Publication number: 20210020608Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.Type: ApplicationFiled: January 16, 2020Publication date: January 21, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jong Youn KIM, Dong Kyu Kim, Jin-Woo Park, Min Jun Bae, Gwang Jae Jeon
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Publication number: 20200273804Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor chip disposed on the first redistribution structure, a plurality of conductive pillars disposed on the first redistribution structure, an encapsulant covering an upper surface of the first redistribution structure, and a second redistribution structure disposed on the encapsulant. The encapsulant has an upper surface having openings that expose upper surface of the plurality of conductive pillars. The second redistribution structure includes a wiring pattern and connection vias connecting the wiring pattern to the plurality of conductive pillars. An inner side surface of an opening extends vertically from a side surface of the conductive pillar.Type: ApplicationFiled: September 11, 2019Publication date: August 27, 2020Inventors: Gwang Jae JEON, Dong Kyu Kim, Jung Ho PARK, Yeon Ho JANG