Patents by Inventor Gwang Kim
Gwang Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12374559Abstract: A semiconductor device has a substrate and a first component disposed over a first surface of the substrate. A connector is disposed over the first surface of the substrate. A first encapsulant is deposited over the first component while the connector remains outside of the first encapsulant. A shielding layer is formed over the first encapsulant while the connector remains outside of the shielding layer. A second component is disposed over a second surface of the substrate. A solder bump is disposed over the second surface of the substrate. A second encapsulant is deposited over the second surface of the substrate. An opening is formed through the second encapsulant to expose the solder bump. A solder ball is disposed in the opening. The solder ball and solder bump are reflowed to form a combined solder bump.Type: GrantFiled: December 18, 2023Date of Patent: July 29, 2025Assignee: STATS ChipPAC Pte. Ltd.Inventors: HunTeak Lee, Gwang Kim, Junho Ye
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Patent number: 12211803Abstract: A semiconductor device has a substrate and an electrical component disposed over a surface of the substrate. An antenna interposer is disposed over the substrate. A first encapsulant is deposited around the antenna interposer. The first encapsulant has a high dielectric constant. The antenna interposer has a conductive layer operating as an antenna and an insulating layer having a low dielectric constant less than the high dielectric constant of the first encapsulant. The antenna interposer is made from an antenna substrate having a plurality of antenna interposers. Bumps are formed over the antenna substrate and the antenna substrate is singulated to make the plurality of antenna interposers. A second encapsulant is deposited over the electrical component. The second encapsulant has a low dielectric constant less than the high dielectric constant of the first encapsulant. A shielding layer is disposed over the second encapsulant.Type: GrantFiled: December 20, 2023Date of Patent: January 28, 2025Assignee: STATS ChipPAC Pte. Ltd.Inventors: HunTeak Lee, Gwang Kim, Junho Ye, YouJoung Choi, MinKyung Kim, Yongwoo Lee, Namgu Kim
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Publication number: 20240290671Abstract: A semiconductor package comprises: a package substrate comprising: a first portion comprising a first conductive pattern extending therewithin having a first thickness; and a second portion comprising a second conductive pattern extending therewithin having a second thickness smaller than the first thickness; at least one electronic component mounted on the second portion and electrically coupled to the second conductive pattern; an encapsulant layer formed on the second portion of the package substrate and covering the at least one electronic component, wherein the encapsulant layer comprises a cavity region; a connector assembly formed within the cavity region of the encapsulant layer and electrically coupled to the second conductive pattern, wherein the connector assembly is exposed from the encapsulant layer to allow for electrical connection with an external device; and a partial shielding layer formed on at least regions other than the cavity region of the encapsulant layer.Type: ApplicationFiled: February 21, 2024Publication date: August 29, 2024Inventors: Gwang KIM, HunTeak LEE
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Publication number: 20240153783Abstract: A semiconductor device has a substrate and a first component disposed over a first surface of the substrate. A connector is disposed over the first surface of the substrate. A first encapsulant is deposited over the first component while the connector remains outside of the first encapsulant. A shielding layer is formed over the first encapsulant while the connector remains outside of the shielding layer. A second component is disposed over a second surface of the substrate. A solder bump is disposed over the second surface of the substrate. A second encapsulant is deposited over the second surface of the substrate. An opening is formed through the second encapsulant to expose the solder bump. A solder ball is disposed in the opening. The solder ball and solder bump are reflowed to form a combined solder bump.Type: ApplicationFiled: December 18, 2023Publication date: May 9, 2024Applicant: STATS ChipPAC Pte. Ltd.Inventors: HunTeak Lee, Gwang Kim, Junho Ye
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Publication number: 20240128201Abstract: A semiconductor device has a substrate and an electrical component disposed over a surface of the substrate. An antenna interposer is disposed over the substrate. A first encapsulant is deposited around the antenna interposer. The first encapsulant has a high dielectric constant. The antenna interposer has a conductive layer operating as an antenna and an insulating layer having a low dielectric constant less than the high dielectric constant of the first encapsulant. The antenna interposer is made from an antenna substrate having a plurality of antenna interposers. Bumps are formed over the antenna substrate and the antenna substrate is singulated to make the plurality of antenna interposers. A second encapsulant is deposited over the electrical component. The second encapsulant has a low dielectric constant less than the high dielectric constant of the first encapsulant. A shielding layer is disposed over the second encapsulant.Type: ApplicationFiled: December 20, 2023Publication date: April 18, 2024Applicant: STATS ChipPAC Pte. Ltd.Inventors: HunTeak Lee, Gwang Kim, Junho Ye, YouJoung Choi, MinKyung Kim, Yongwoo Lee, Namgu Kim
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Patent number: 11894314Abstract: A semiconductor device has a substrate and an electrical component disposed over a surface of the substrate. An antenna interposer is disposed over the substrate. A first encapsulant is deposited around the antenna interposer. The first encapsulant has a high dielectric constant. The antenna interposer has a conductive layer operating as an antenna and an insulating layer having a low dielectric constant less than the high dielectric constant of the first encapsulant. The antenna interposer is made from an antenna substrate having a plurality of antenna interposers. Bumps are formed over the antenna substrate and the antenna substrate is singulated to make the plurality of antenna interposers. A second encapsulant is deposited over the electrical component. The second encapsulant has a low dielectric constant less than the high dielectric constant of the first encapsulant. A shielding layer is disposed over the second encapsulant.Type: GrantFiled: September 10, 2021Date of Patent: February 6, 2024Assignee: STATS ChipPAC Pte. Ltd.Inventors: HunTeak Lee, Gwang Kim, Junho Ye, YouJoung Choi, MinKyung Kim, Yongwoo Lee, Namgu Kim
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Patent number: 11887863Abstract: A semiconductor device has a substrate and a first component disposed over a first surface of the substrate. A connector is disposed over the first surface of the substrate. A first encapsulant is deposited over the first component while the connector remains outside of the first encapsulant. A shielding layer is formed over the first encapsulant while the connector remains outside of the shielding layer. A second component is disposed over a second surface of the substrate. A solder bump is disposed over the second surface of the substrate. A second encapsulant is deposited over the second surface of the substrate. An opening is formed through the second encapsulant to expose the solder bump. A solder ball is disposed in the opening. The solder ball and solder bump are reflowed to form a combined solder bump.Type: GrantFiled: September 7, 2021Date of Patent: January 30, 2024Assignee: STATS ChipPAC Pte. Ltd.Inventors: HunTeak Lee, Gwang Kim, Junho Ye
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Publication number: 20230081706Abstract: A semiconductor device has a substrate and an electrical component disposed over a surface of the substrate. An antenna interposer is disposed over the substrate. A first encapsulant is deposited around the antenna interposer. The first encapsulant has a high dielectric constant. The antenna interposer has a conductive layer operating as an antenna and an insulating layer having a low dielectric constant less than the high dielectric constant of the first encapsulant. The antenna interposer is made from an antenna substrate having a plurality of antenna interposers. Bumps are formed over the antenna substrate and the antenna substrate is singulated to make the plurality of antenna interposers. A second encapsulant is deposited over the electrical component. The second encapsulant has a low dielectric constant less than the high dielectric constant of the first encapsulant. A shielding layer is disposed over the second encapsulant.Type: ApplicationFiled: September 10, 2021Publication date: March 16, 2023Applicant: STATS ChipPAC Pte. Ltd.Inventors: HunTeak Lee, Gwang Kim, Junho Ye, YouJoung Choi, MinKyung Kim, Yongwoo Lee, Namgu Kim
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Publication number: 20230074430Abstract: A semiconductor device has a substrate and a first component disposed over a first surface of the substrate. A connector is disposed over the first surface of the substrate. A first encapsulant is deposited over the first component while the connector remains outside of the first encapsulant. A shielding layer is formed over the first encapsulant while the connector remains outside of the shielding layer. A second component is disposed over a second surface of the substrate. A solder bump is disposed over the second surface of the substrate. A second encapsulant is deposited over the second surface of the substrate. An opening is formed through the second encapsulant to expose the solder bump. A solder ball is disposed in the opening. The solder ball and solder bump are reflowed to form a combined solder bump.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Applicant: STATS ChipPAC Pte. Ltd.Inventors: HunTeak Lee, Gwang Kim, Junho Ye
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Patent number: 9877606Abstract: According to an embodiment of the present invention, a tea infuser comprises a hollow body substantially shaped as a truncated cone. The body includes an upper part having an internal thread. A container is threaded into the body through the upper part. A lower part has an external thread. A filter is disposed in the body. The filter has a jaw along an outer circumferential surface thereof. A first cap covers the upper part. A second cap is threaded to the lower part.Type: GrantFiled: April 9, 2015Date of Patent: January 30, 2018Inventors: Gwang Kim, Sung Won Yoo, Dong Ok Ha
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Patent number: 9704857Abstract: A semiconductor device has a substrate and RF FEM formed over the substrate. The RF FEM includes an LC low-pass filter having an input coupled for receiving a transmit signal. A Tx/Rx switch has a first terminal coupled to an output of the LC filter. A diplexer has a first terminal coupled to a second terminal of the Tx/Rx switch and a second terminal for providing an RF signal. An IPD band-pass filter has an input coupled to a third terminal of the Tx/Rx switch and an output providing a receive signal. The LC filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The IPD filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The RF FEM substrate can be stacked over a semiconductor package containing an RF transceiver.Type: GrantFiled: November 15, 2012Date of Patent: July 11, 2017Assignee: STATS ChipPAC, Pte. Ltd.Inventors: HyunTai Kim, YongTaek Lee, Gwang Kim, ByungHoon Ahn, Kai Liu
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Publication number: 20160296057Abstract: According to an embodiment of the present invention, a tea infuser comprises a hollow body substantially shaped as a truncated cone. The body includes an upper part having an internal thread. A container is threaded into the body through the upper part. A lower part has an external thread. A filter is disposed in the body. The filter has a jaw along an outer circumferential surface thereof. A first cap covers the upper part. A second cap is threaded to the lower part.Type: ApplicationFiled: April 9, 2015Publication date: October 13, 2016Inventors: Gwang KIM, Sung Won YOO, Dong Ok HA
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Patent number: 9190340Abstract: A semiconductor device has a first semiconductor die containing a low pass filter and baluns. The first semiconductor die has a high resistivity substrate. A second semiconductor die including a bandpass filter is mounted to the first semiconductor die. The second semiconductor die has a gallium arsenide substrate. A third semiconductor die including an RF switch is mounted to the first semiconductor die. A fourth semiconductor die includes an RF transceiver. The first, second, and third semiconductor die are mounted to the fourth semiconductor die. The first, second, third, and fourth semiconductor die are mounted to a substrate. An encapsulant is deposited over the first, second, third, and fourth semiconductor die and substrate. A plurality of bond wires is formed between the second semiconductor die and first semiconductor die, and between the third semiconductor die and first semiconductor die, and between the first semiconductor die and substrate.Type: GrantFiled: June 17, 2011Date of Patent: November 17, 2015Assignee: STATS ChipPAC, Ltd.Inventors: YongTaek Lee, HyunTai Kim, Gwang Kim, ByungHoon Ahn, Kai Liu
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Patent number: 9082638Abstract: A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements.Type: GrantFiled: August 10, 2012Date of Patent: July 14, 2015Assignee: STATS ChipPAC, Ltd.Inventors: YongTaek Lee, Gwang Kim, ByungHoon Ahn
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Patent number: 8896115Abstract: A semiconductor wafer has an insulating layer over a first surface of the substrate. An IPD structure is formed over the insulating layer. The IPD structure includes a MIM capacitor and inductor. A conductive via is formed through a portion of the IPD structure and partially through the substrate. The conductive via can be formed in first and second portions. The first portion is formed partially through the substrate and second portion is formed through a portion of the IPD structure. A first via is formed through a second surface of the substrate to the conductive via. A shielding layer is formed over the second surface of the substrate wafer. The shielding layer extends into the first via to the conductive via. The shielding layer is electrically connected through the conductive via to an external ground point. The semiconductor wafer is singulated through the conductive via.Type: GrantFiled: April 3, 2012Date of Patent: November 25, 2014Assignee: STATS ChipPAC, Ltd.Inventors: YongTaek Lee, HyunTai Kim, Gwang Kim, ByungHoon Ahn
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Patent number: 8481371Abstract: A method of manufacture of a thin package system with external terminals includes: providing a leadframe; providing a template for defining an external bond finger; forming external bond fingers in the template on the leadframe; forming land pad terminals by a first multi-layer plating; providing a die; attaching the die to the land pad terminals above the leadframe with an adhesive on the leadframe; covering an encapsulant over at least portions of the die and the external bond fingers; and removing the leadframe leaving a surface of the adhesive coplanar with a surface of the encapsulant.Type: GrantFiled: May 20, 2011Date of Patent: July 9, 2013Assignee: STATS Chippac Ltd.Inventors: Youngcheol Kim, Myung Kil Lee, Gwang Kim, Koo Hong Lee
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Patent number: 8349648Abstract: A semiconductor device has a substrate and RF FEM formed over the substrate. The RF FEM includes an LC low-pass filter having an input coupled for receiving a transmit signal. A Tx/Rx switch has a first terminal coupled to an output of the LC filter. A diplexer has a first terminal coupled to a second terminal of the Tx/Rx switch and a second terminal for providing an RF signal. An IPD band-pass filter has an input coupled to a third terminal of the Tx/Rx switch and an output providing a receive signal. The LC filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The IPD filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The RF FEM substrate can be stacked over a semiconductor package containing an RF transceiver.Type: GrantFiled: June 15, 2010Date of Patent: January 8, 2013Assignee: STATS ChipPAC, Ltd.Inventors: HyunTai Kim, YongTaek Lee, Gwang Kim, ByungHoon Ahn, Kai Liu
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Publication number: 20120319302Abstract: A semiconductor device has a first semiconductor die containing a low pass filter and baluns. The first semiconductor die has a high resistivity substrate. A second semiconductor die including a bandpass filter is mounted to the first semiconductor die. The second semiconductor die has a gallium arsenide substrate. A third semiconductor die including an RF switch is mounted to the first semiconductor die. A fourth semiconductor die includes an RF transceiver. The first, second, and third semiconductor die are mounted to the fourth semiconductor die. The first, second, third, and fourth semiconductor die are mounted to a substrate. An encapsulant is deposited over the first, second, third, and fourth semiconductor die and substrate. A plurality of bond wires is formed between the second semiconductor die and first semiconductor die, and between the third semiconductor die and first semiconductor die, and between the first semiconductor die and substrate.Type: ApplicationFiled: June 17, 2011Publication date: December 20, 2012Applicant: STATS CHIPPAC, LTD.Inventors: YongTaek Lee, HyunTai Kim, Gwang Kim, ByungHoon Ahn, Kai Liu
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Publication number: 20120299149Abstract: A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements.Type: ApplicationFiled: August 10, 2012Publication date: November 29, 2012Applicant: STATS CHIPPAC, LTD.Inventors: YongTaek Lee, Gwang Kim, ByungHoon Ahn
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Patent number: 8269308Abstract: A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements.Type: GrantFiled: March 19, 2008Date of Patent: September 18, 2012Assignee: STATS ChipPAC, Ltd.Inventors: YongTaek Lee, Gwang Kim, ByungHoon Ahn