Patents by Inventor Gwang Min CHA

Gwang Min CHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240023406
    Abstract: A display device includes: a substrate; a transistor on the substrate; a first electrode connected to the transistor; a first partition wall on the first electrode, and having a pixel opening; an auxiliary electrode on the first partition wall; a second partition wall on the auxiliary electrode; an emission layer in the pixel opening; and a second electrode on the emission layer and the second partition wall, and connected to the auxiliary electrode. An end portion of the auxiliary electrode protrudes from a side surface of at least one of the first partition wall or the second partition wall.
    Type: Application
    Filed: March 16, 2023
    Publication date: January 18, 2024
    Inventors: Jun Gi KIM, HYE SUN KIM, Sang Hyun YUN, Gwang Min CHA
  • Patent number: 10629832
    Abstract: A display device includes a substrate, a semiconductor layer disposed on the substrate, a first insulating layer disposed on the semiconductor layer, a first conductive layer disposed on the first insulating layer and electrically connected to the semiconductor layer via a first contact hole, which is defined through the first insulating layer, a second insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the second insulating layer and electrically connected to the first conductive layer via a second contact hole, which is defined through the second insulating layer, where the first and second contact holes overlap each other, and a residual layer, which includes a portion of the second insulating layer, is disposed in the first contact hole.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG DISPLAY CO. LTD.
    Inventors: Jun Hong Park, Jung Soo Lee, Gwang Min Cha, Jeong Min Park
  • Patent number: 10497812
    Abstract: A transistor is positioned on a substrate. The transistor includes a semiconductor layer. A buffer layer is positioned between the substrate and the semiconductor layer of the transistor, including an insulating material. A bottom layer is positioned between the substrate and the buffer layer. The bottom layer and the semiconductor layer overlap each other. The bottom layer includes a first layer, a second layer, and a third layer that are stacked on each other in a direction away from the substrate.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: December 3, 2019
    Assignee: SAMSUMG DISPLAY CO., LTD.
    Inventors: Dong Hee Lee, Gwang Min Cha, Dong Min Lee
  • Publication number: 20190109289
    Abstract: A display device includes a substrate, a semiconductor layer disposed on the substrate, a first insulating layer disposed on the semiconductor layer, a first conductive layer disposed on the first insulating layer and electrically connected to the semiconductor layer via a first contact hole, which is defined through the first insulating layer, a second insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the second insulating layer and electrically connected to the first conductive layer via a second contact hole, which is defined through the second insulating layer, where the first and second contact holes overlap each other, and a residual layer, which includes a portion of the second insulating layer, is disposed in the first contact hole.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 11, 2019
    Inventors: Jun Hong PARK, Jung Soo LEE, Gwang Min CHA, Jeong Min PARK
  • Patent number: 10181570
    Abstract: A display device includes a substrate, a semiconductor layer disposed on the substrate, a first insulating layer disposed on the semiconductor layer, a first conductive layer disposed on the first insulating layer and electrically connected to the semiconductor layer via a first contact hole, which is defined through the first insulating layer, a second insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the second insulating layer and electrically connected to the first conductive layer via a second contact hole, which is defined through the second insulating layer, where the first and second contact holes overlap each other, and a residual layer, which includes a portion of the second insulating layer, is disposed in the first contact hole.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 15, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun Hong Park, Jung Soo Lee, Gwang Min Cha, Jeong Min Park
  • Publication number: 20180358570
    Abstract: A display device includes a substrate, a semiconductor layer disposed on the substrate, a first insulating layer disposed on the semiconductor layer, a first conductive layer disposed on the first insulating layer and electrically connected to the semiconductor layer via a first contact hole, which is defined through the first insulating layer, a second insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the second insulating layer and electrically connected to the first conductive layer via a second contact hole, which is defined through the second insulating layer, where the first and second contact holes overlap each other, and a residual layer, which includes a portion of the second insulating layer, is disposed in the first contact hole.
    Type: Application
    Filed: November 30, 2017
    Publication date: December 13, 2018
    Inventors: Jun Hong PARK, Jung Soo LEE, Gwang Min CHA, Jeong Min PARK
  • Publication number: 20170358688
    Abstract: A transistor is positioned on a substrate. The transistor includes a semiconductor layer. A buffer layer is positioned between the substrate and the semiconductor layer of the transistor, including an insulating material. A bottom layer is positioned between the substrate and the buffer layer. The bottom layer and the semiconductor layer overlap each other. The bottom layer includes a first layer, a second layer, and a third layer that are stacked on each other in a direction away from the substrate.
    Type: Application
    Filed: February 17, 2017
    Publication date: December 14, 2017
    Inventors: DONG HEE LEE, GWANG MIN CHA, DONG MIN LEE
  • Patent number: 9824788
    Abstract: Provided is a metal wire. The metal wire includes a copper layer, and at least one barrier layer. The barrier layer is disposed on at least one of an upper part and a lower part of the copper layer. The barrier layer includes an alloy including copper, nickel, and zinc.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: November 21, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Su Hyoung Kang, Sang Woo Sohn, Chang Oh Jeong, Gwang Min Cha
  • Patent number: 9786694
    Abstract: A display device and a method of manufacturing the display device are provided. According to an exemplary embodiment, a display device includes: a substrate; a gate electrode disposed on the substrate; a semiconductor pattern disposed on the gate electrode; data wiring disposed on the semiconductor pattern and having a data line, a source electrode, and a drain electrode; a first barrier layer disposed between the data wiring and the semiconductor pattern; and undercuts disposed on at least one side of each segment of the first barrier layer.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: October 10, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gwang Min Cha, Su Kyoung Yang, Chan Woo Yang
  • Patent number: 9773823
    Abstract: A display device and a method of manufacturing the display device are disclosed. In one aspect, the method includes forming a sacrificial layer over a carrier substrate, forming a passivation barrier layer to cover upper and lateral sides of the sacrificial layer and forming a thin film transistor layer over the passivation barrier layer. The method also includes placing a mask over the thin film transistor layer so as to expose an edge portion of the passivation barrier layer, wherein the edge portion does not overlap the mask in the depth dimension of the display device. The method further includes removing the edge portion of the passivation barrier layer so as to form a barrier layer and separating the carrier substrate from the barrier layer via the sacrificial layer.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: September 26, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su-Hyoung Kang, Gwang Min Cha, Chang Oh Jeong
  • Publication number: 20170179262
    Abstract: A thin film transistor array panel that includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode; a metal oxide layer covering the source electrode and the drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer, wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and metal included in the metal oxide layer is formed by diffusing the second material.
    Type: Application
    Filed: March 1, 2017
    Publication date: June 22, 2017
    Inventors: Hyun Ju KANG, Dong Hee LEE, Gwang Min CHA, Sang Won SHIN, Sang Woo SOHN
  • Publication number: 20170117298
    Abstract: A display device and a method of manufacturing the display device are provided. According to an exemplary embodiment, a display device includes: a substrate; a gate electrode disposed on the substrate; a semiconductor pattern disposed on the gate electrode; data wiring disposed on the semiconductor pattern and having a data line, a source electrode, and a drain electrode; a first barrier layer disposed between the data wiring and the semiconductor pattern; and undercuts disposed on at least one side of each segment of the first barrier layer.
    Type: Application
    Filed: September 13, 2016
    Publication date: April 27, 2017
    Inventors: Gwang Min CHA, Su Kyoung YANG, Chan Woo YANG
  • Patent number: 9627548
    Abstract: A thin film transistor array panel that includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode; a metal oxide layer covering the source electrode and the drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer, wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and metal included in the metal oxide layer is formed by diffusing the second material.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: April 18, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Ju Kang, Dong Hee Lee, Gwang Min Cha, Sang Won Shin, Sang Woo Sohn
  • Publication number: 20160315227
    Abstract: A display device and a method of manufacturing the display device are disclosed. In one aspect, the method includes forming a sacrificial layer over a carrier substrate, forming a passivation barrier layer to cover upper and lateral sides of the sacrificial layer and forming a thin film transistor layer over the passivation barrier layer. The method also includes placing a mask over the thin film transistor layer so as to expose an edge portion of the passivation barrier layer, wherein the edge portion does not overlap the mask in the depth dimension of the display device. The method further includes removing the edge portion of the passivation barrier layer so as to form a barrier layer and separating the carrier substrate from the barrier layer via the sacrificial layer.
    Type: Application
    Filed: November 23, 2015
    Publication date: October 27, 2016
    Inventors: Su-Hyoung Kang, Gwang Min Cha, Chang Oh Jeong
  • Publication number: 20160197192
    Abstract: A thin film transistor array panel that includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode; a metal oxide layer covering the source electrode and the drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer, wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and metal included in the metal oxide layer is formed by diffusing the second material.
    Type: Application
    Filed: August 31, 2015
    Publication date: July 7, 2016
    Inventors: Hyun Ju KANG, Dong Hee LEE, Gwang Min CHA, Sang Won SHIN, Sang Woo SOHN
  • Publication number: 20160133348
    Abstract: Provided is a metal wire. The metal wire includes a copper layer, and at least one barrier layer. The barrier layer is disposed on at least one of an upper part and a lower part of the copper layer. The barrier layer includes an alloy including copper, nickel, and zinc.
    Type: Application
    Filed: March 17, 2015
    Publication date: May 12, 2016
    Inventors: Su Hyoung KANG, Sang Woo SOHN, Chang Oh JEONG, Gwang Min CHA