Abstract: Disclosed is a chalcogenide material including germanium (Ge), selenium (Se), arsenic (As), silicon (Si) and indium (In). In the chalcogenide material, a content of selenium (Se) is 49 at % to 56 at %, a content of indium (In) is 1.1 at % or less, and a sum of contents of germanium (Ge) and silicon (Si) is 18 at % to 21 at %.

Abstract: A semiconductor memory device includes a memory cell interposed between a first electrode and a second electrode, and configured with a chalcogenide layer that includes three or more components, and a peripheral circuit for providing the memory cell with a program pulse inducing a compositional gradient in the chalcogenide layer.

Abstract: A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 13 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 13 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 13 element.

Abstract: A PVD chamber shield includes: a shield configured to surround a space between a sputtering target and a substrate that are disposed in a PVD chamber body, the shield having a hollow shape with an inner surface and an outer surface; and a coating layer formed over the inner surface of the shield. The coating layer has i) a dielectric constant not greater than a dielectric constant of a material deposited over the substrate, ii) a porosity greater than 0 vol % and less than 100 vol %, and iii) a thickness greater than 150 pm and less than a given upper limit, the upper limit being set to prevent an occurrence of peeling of a material deposited over the coating layer.

Abstract: A semiconductor device may include a first electrode, a second electrode, an insulating layer interposed between the first electrode and the second electrode and including an opening having an inclined sidewall, a variable resistance layer formed in the opening, and a liner interposed between the variable resistance layer and the insulating layer and between the variable resistance layer and the first electrode. The variable resistance layer includes a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area. The variable resistance layer maintains an amorphous state during a program operation.

Abstract: A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 3 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 3 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 3 element.

Abstract: A chalcogenide material and an electronic device are provided. The chalcogenide material may include 0.1-5 atomic percent (at %) of silicon, 15-22 at % of germanium, 30-35 at % of arsenic and 40-50 at % of selenium. The electronic device may include a semiconductor memory device, the semiconductor memory device including a first memory cell that includes a first switching element. The first switching element may include a chalcogenide material including 0.1-5 atomic percent (at %) of silicon, 15-22 at % of germanium, 30-35 at % of arsenic, and 40-50 at % of selenium.

Abstract: A chalcogenide material and an electronic device are provided. The chalcogenide material may include 0.1-5 atomic percent (at %) of silicon, 15-22 at % of germanium, 30-35 at % of arsenic and 40-50 at % of selenium. The electronic device may include a semiconductor memory device, the semiconductor memory device including a first memory cell that includes a first switching element. The first switching element may include a chalcogenide material including 0.1-5 atomic percent (at %) of silicon, 15-22 at % of germanium, 30-35 at % of arsenic, and 40-50 at % of selenium.