Abstract: A receiver for FSK signals produces quadrature related first and second frequency down-converted difference signals (I and Q), which are amplitude limited to form respectively first and second square wave signals. The first and second square wave signals are sampled at changes in polarity of the second and first square wave signals, combined and fed to a memory, for example a hysteresis circuit, responsive to a change in polarity in the combined signal for producing a first substantially constant dc output until the next following change in polarity is detected whereupon a second substantially constant dc output is produced. By using a memory rather than a filter, reactive components are avoided making it less expensive to integrate. Also, a fixed level bit slicer can be used.