Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, a controller includes PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption. In these and other embodiments, a window comparator structure is provided that is capable of generating control signals for use in buck, boost and buck-boost modes of operation.

Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, a controller includes PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption. In these and other embodiments, the controller includes a low-Iq synthetic ripple generator for use in implementing hysteretic control of a buck-boost controller.

Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, an asynchronous controller of a buck-boost converter implements a state diagram for controlling PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption.

Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, a controller includes PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption. In these and other embodiments, a window comparator structure is provided that is capable of generating control signals for use in buck, boost and buck-boost modes of operation.

Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, a controller includes PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption. In these and other embodiments, the controller includes a low-Iq synthetic ripple generator for use in implementing hysteretic control of a buck-boost controller.

Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, a controller includes PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption. In these and other embodiments, the controller includes a low-Iq synthetic ripple generator for use in implementing hysteretic control of a buck-boost controller.

Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, a controller includes PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption. In these and other embodiments, a window comparator structure is provided that is capable of generating control signals for use in buck, boost and buck-boost modes of operation.

Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, an asynchronous controller of a buck-boost converter implements a state diagram for controlling PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption.

Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, a controller includes PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption. In these and other embodiments, the controller includes a low-Iq synthetic ripple generator for use in implementing hysteretic control of a buck-boost controller.

Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, a controller includes PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption. In these and other embodiments, a window comparator structure is provided that is capable of generating control signals for use in buck, boost and buck-boost modes of operation.

Abstract: A buffer stage includes a flipped voltage follower and an emitter follower. The flipped voltage follower is connected between a high voltage rail and a low voltage rail and includes an input and an output. The emitter follower is also connected between the high voltage rail and the low voltage rail and includes an input and an output. A resistor connects the output of the flipped voltage follower to the output of the emitter follower. The input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage. The output of the emitter follower provides an output of the buffer stage. A differential buffer stage can be implemented using a pair of such buffer stages. Such a differential buffer stage can provide the output stage for a fully differential operational amplifier.

Abstract: A buffer stage includes a flipped voltage follower and an emitter follower. The flipped voltage follower is connected between a high voltage rail and a low voltage rail and includes an input and an output. The emitter follower is also connected between the high voltage rail and the low voltage rail and includes an input and an output. A resistor connects the output of the flipped voltage follower to the output of the emitter follower. The input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage. The output of the emitter follower provides an output of the buffer stage. A differential buffer stage can be implemented using a pair of such buffer stages. Such a differential buffer stage can provide the output stage for a fully differential operational amplifier.

Abstract: A buffer stage includes a flipped voltage follower and an emitter follower. The flipped voltage follower is connected between a high voltage rail and a low voltage rail and include an input and an output. The emitter follower is also connected between the high voltage rail and the low voltage rail and includes an input and an output. A resistor connects the output of the flipped voltage follower to the output of the emitter follower. The input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage. The output of the emitter follower provides an output of the buffer stage. A differential buffer stage can be implemented using a pair of such buffer stages. Such a differential buffer stage can provide the output stage for a fully differential operational amplifier.

Abstract: A buffer stage includes a flipped voltage follower and an emitter follower. The flipped voltage follower is connected between a high voltage rail and a low voltage rail and include an input and an output. The emitter follower is also connected between the high voltage rail and the low voltage rail and includes an input and an output. A resistor connects the output of the flipped voltage follower to the output of the emitter follower. The input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage. The output of the emitter follower provides an output of the buffer stage. A differential buffer stage can be implemented using a pair of such buffer stages. Such a differential buffer stage can provide the output stage for a fully differential operational amplifier.

Abstract: A chopper stabilized amplifier has differential inputs, an output, and a low frequency path and a high frequency path from the differential inputs to the output. Chopping occurs, at a chopping frequency, of a differential signal at differential inputs and outputs of an amplifier stage of the low frequency path to thereby produce a chopped differential signal that has a DC offset of the amplifier stage frequency shifted up to the chopping frequency. A continuous time filter embedded between a pair of further amplifier stages of the low frequency path is used to attenuate chopper frequency ripple resulting from the chopping at the chopping frequency. Additionally, a buffer is used to allow feedback through a compensation capacitor for the low frequency path, yet prevent chopper frequency ripple from feeding forward through the compensation capacitor to the output of the amplifier.

Abstract: A chopper stabilized amplifier has differential inputs, an output, and a low frequency path and a high frequency path from the differential inputs to the output. Chopping occurs, at a chopping frequency, of a differential signal at differential inputs and outputs of an amplifier stage of the low frequency path to thereby produce a chopped differential signal that has a DC offset of the amplifier stage frequency shifted up to the chopping frequency. A continuous time filter embedded between a pair of further amplifier stages of the low frequency path is used to attenuate chopper frequency ripple resulting from the chopping at the chopping frequency. Additionally, a buffer is used to allow feedback through a compensation capacitor for the low frequency path, yet prevent chopper frequency ripple from feeding forward through the compensation capacitor to the output of the amplifier.

Abstract: A radio transceiver comprises a reception path, a transmission path, and a frequency generator with a programmable phase lock loop. The reception path, the transmission path, and the frequency generator share a maximum amount of common circuitry to facilitate implementation of the entire radio transceiver on a single integrated circuit. The reception path includes an amplifier and a quadrature mixer for producing low intermediate frequency signals. The transmission path can be controlled by either a modulated voltage controlled transmitter or an in-phase and quadrature modulator transmitter.

Abstract: The mixer circuit is a singled ended input to a double balanced high dynamic range mixer with only two base-emitter junctions across the supply. It provides for the use of bondwires to off chip ground as DC block and DC feed elements. The single ended input and differential output balanced mixer is well suited for the input stage of an integrated radio receiver—off chip circuitry is usually single ended, but on chip circuits are usually differential. No off chip differential RF circuits or baluns are required which reduces off chip component count and improves radio performance. The mixer circuit has lower LO drive requirements because of the DC coupled LO port. This results in better radio performance and a smaller die area because of the DC coupled IF port.

Abstract: A data recovery algorithm for implementation in a radio transmitter or receiver that includes a direct current level setting circuit with a preamble detector which will establish a threshold for a simplified decision simplified equalizer slicer that improves receiver performance in a feedback manner by utilizing an analog comparator, a one symbol long one bit resolution delay line and a summing junction.

Abstract: A digital phase quantized frequency modulation (FM) detector (300) is for a communication receiver (100). A digital phase FM quantizer receives (310) I and Q signals (221, 222) derived from a received FM signal (119) and generates a coded position word (381) of width M bits at the beginning of each period of a sample clock (190) that identifies a sector location of a phasor representing the I and Q signals. A two's complement converter (400) converts the coded position word into a two's complement position word of width M bits. A differentiator (420) of width M bits generates a two's complement difference word which represents a change of a phase angle of the phasor in magnitude and direction during each period of the sample clock. A digital post detection filter filters consecutive two's complement difference words and generates therefrom a reconstructed digital demodulated signal (461).