Patents by Inventor Gwo-Chyuan KUO

Gwo-Chyuan KUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of chip packaging
    Patent number: 9761486
    Abstract: A method of forming a chip package portion having a reduced loading effect between various metal lines during a leveling process comprises forming a first layer, a passivation layer over the first layer, a second layer over the passivation layer, and a third layer over the second layer. The method also comprises forming a patterned opening having multiple depths by removing portions of the first layer, the passivation layer, the second layer, and the third layer by way of one or more removal processes that remove portions of the first layer, the passivation layer, the second layer, and the third layer in accordance with one or more patterned photoresist depositions. The method further comprises depositing a material into the patterned opening, and leveling the material deposited into the patterned opening.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gwo-Chyuan Kuo, Han-Wei Yang, Chen-Chung Lai
  • CHIP PACKAGE, USE AND METHOD OF MAKING THEREO
    Publication number: 20150279769
    Abstract: A method of forming a chip package portion having a reduced loading effect between various metal lines during a leveling process comprises forming a first layer, a passivation layer over the first layer, a second layer over the passivation layer, and a third layer over the second layer. The method also comprises forming a patterned opening having multiple depths by removing portions of the first layer, the passivation layer, the second layer, and the third layer by way of one or more removal processes that remove portions of the first layer, the passivation layer, the second layer, and the third layer in accordance with one or more patterned photoresist depositions.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gwo-Chyuan KUO, Han-Wei YANG, Chen-Chung LAI