Abstract: A pixel-data processing circuit adapted to resize pixel data in a first vertically processing mode is reconfigurable to operate in a nonresizing mode, wherein each mode receives pixel data at a first pixel rate and outputs pixel data at a different pixel rate. In one particular example embodiment, pixels are received at two pixels per cycle and output to a storage unit at one pixel per cycle. In a first operational resizing mode, the embodiment includes vertically processing pixel data including polyphase filtering and line-buffering the pixel data, resizing the received pixel data by circulating the data in the line buffers and by filtering the circulated data for the polyphase filtering, and presenting resized pixel data for storage at the first pixel rate. In a second operational nonresizing mode, the pixel data is processed by double-line buffering the pixel data, bypassing the polyphase filtering, and presenting nonresized pixel data for storage at the rate of one pixel per cycle.

Abstract: A pixel-data processing circuit adapted to resize pixel data in a first vertically processing mode is reconfigurable to operate in a nonresizing mode, wherein each mode receives pixel data at a first pixel rate and outputs pixel data at a different pixel rate. In one particular example embodiment, pixels are received at two pixels per cycle and output to a storage unit at one pixel per cycle. In a first operational resizing mode, the embodiment includes vertically processing pixel data including polyphase filtering and line-buffering the pixel data, resizing the received pixel data by circulating the data in the line buffers and by filtering the circulated data for the polyphase filtering, and presenting resized pixel data for storage at the first pixel rate. In a second operational nonresizing mode, the pixel data is processed by double-line buffering the pixel data, bypassing the polyphase filtering, and presenting nonresized pixel data for storage at the rate of one pixel per cycle.

Abstract: According to an example embodiment, the present invention is directed to pixel-data processing that includes scanning a first 2×2 line in each of a series of immediately adjacent pixel blocks, prior to scanning a second 2×2 line in each of the series of pixel blocks. Each scanned line is then processed for motion compensation in a manner that addresses challenges, including those discussed above, related to buffer size requirements, power consumption requirements and latency.