Abstract: A current-switching method and circuit is provided for use with digital-to-analog converters (DACs) to provide improved compliance and linearity in the output current characteristic. In the current-switching circuit, an additional transistor that is set to a permanently-on state is connected at the output port of the current-switching circuit, which can help increase the output impedance of the current-switching circuit. Moreover, the problem of simultaneous switching-off of two control transistors can be eliminated by connecting the gate of one transistor to a reference voltage whose magnitude is set between the logic-high and logic-low voltage states of the input digital signal. The current-switching method and circuit can therefore meet the requirements of 3 V working voltage with 1.2 V output compliance and the requirements of 10 bits linearity in the output current characteristic.

Abstract: A circuit for monitoring battery voltages of a telephone terminal facility is disclosed. This circuit mainly includes a ringing detection circuit for generating a pulse signal in response to an off-hook signal or a ringing signal, a power detecting circuit for detecting battery voltages and a latch being in series connection with the power detecting circuit for outputting a signal showing a status of the detected battery voltages. The power detecting circuit and the latch are of an edge-triggered type and are activated only when a handset of a telephone is picked up or a ringing signal is received so that both the consumed power and the voltage variations are low.

Abstract: An offset-free switched capacitor circuit selectively operated by a non-overlapping two-phase clock signal for processing a frequency shift keying (FSK) input signal is provided. The switched capacitor circuit includes a filter which inputs a voltage signal for generating an output signal which assumes a first voltage value Vt1 at the first phase of the clock signal and assumes a second voltage value Vt2 at the second phase of the clock signal. The output signal of the switched capacitor circuit is an input to a succeeding hysteresis limiter. The hysteresis limiter, which receives the difference of Vt2 and Vt1, is operative to generate a logic signal which is HIGH when an input signal thereof exceeds a HIGH.sub.-- ref signal and is LOW when the input signal thereof falls below a LOW.sub.-- ref signal, and is so operated that the offset voltage associated with the amplifier therein is counterbalanced via internal operation.