Patents by Inventor Gwon Ho Ryu

Gwon Ho Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120076294
    Abstract: Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key; and a round function calculator for generating encrypted/decrypted data using input data and the round key. Here, the round function calculator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms.
    Type: Application
    Filed: December 6, 2011
    Publication date: March 29, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Bon Seok KOO, Gwon Ho RYU, Sang Woon YANG, Tae Joo CHANG
  • Patent number: 8094815
    Abstract: Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key; and a round function calculator for generating encrypted/decrypted data using input data and the round key. Here, the round function calculator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: January 10, 2012
    Assignee: Electronics andTelecommunications Research Institute
    Inventors: Bon Seok Koo, Gwon Ho Ryu, Sang Woon Yang, Tae Joo Chang
  • Publication number: 20090147946
    Abstract: Provided is an apparatus for computing a T-function based Stream Cipher (TSC)-4 stream cipher. The apparatus includes: two T-function units; and a nonlinear filter for receiving bits output from the two T-function units and generating an 8-bit output sequence per clock. Each of the T-function units includes: a first register for storing an internal state value of the lower N bits; an N-bit internal state updater for updating the internal state value of the lower N-bits stored in the first register; an intermediate result register for storing an intermediate result value output from the N-bit internal state updater; a second register for storing an internal state value of the upper M bits; and an M-bit internal state updater for updating the internal state value of the upper M bits stored in the second register using the value stored in the intermediate result register.
    Type: Application
    Filed: November 13, 2008
    Publication date: June 11, 2009
    Inventors: Gwon Ho RYU, Dong Wook LEE, Bon Seok KOO, Tae Joo CHANG
  • Publication number: 20080112560
    Abstract: Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key; and a round function calculator for generating encrypted/decrypted data using input data and the round key. Here, the round function calculator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms.
    Type: Application
    Filed: October 25, 2007
    Publication date: May 15, 2008
    Inventors: Bon Seok KOO, Gwon Ho RYU, Sang Woon YANG, Tae Joo CHANG