Patents by Inventor Gwyn Robert Jones

Gwyn Robert Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7944746
    Abstract: Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: May 17, 2011
    Assignee: Spansion LLC
    Inventors: Gwyn Robert Jones, Mark W Randolph, John Darilek, Sean O'Mullan, Jacob Marcantel, Rick Anundson, Adam Shackleton, Xiaojian Chu, Abhijit Raghunathan, Asif Arfi, Gulzar Ahmed Kathawala, Zhizheng Liu, Sung-Chul Lee
  • Patent number: 7619932
    Abstract: Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: November 17, 2009
    Assignee: Spansion LLC
    Inventors: Gwyn Robert Jones, Edward Franklin Runnion, Zhizheng Liu, Mark William Randolph
  • Publication number: 20090189212
    Abstract: An electronic device includes a memory cell. The memory cell includes a semiconductor region, a first current-carrying electrode adjacent to the semiconductor region, and a first dopant-containing region adjacent to a first current-carrying electrode. The semiconductor region includes a Group 14 atom and the first dopant-containing region includes a Group 13 atom. The Group 13 atom has an atomic number greater than the atomic number of the Group 14 atom.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Applicant: SPANSION LLC
    Inventors: Gwyn Robert Jones, Mark Randolph
  • Publication number: 20090154251
    Abstract: Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 18, 2009
    Applicant: SPANSION LLC
    Inventors: Gwyn Robert Jones, Edward Franklin Runnion, Zhizheng Liu, Mark William Randolph
  • Publication number: 20090135659
    Abstract: Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 28, 2009
    Applicant: SPANSION LLC
    Inventors: Gwyn Robert Jones, Mark W. Randolph, John Darilek, Sean O'Mullan, Jacob Marcantel, Rick Anundson, Adam Shackleton, Xiaojian Chu, Abhijit Raghunathan, Asif Arfi, Gulzar Ahmed Kathawala, Zhizheng Liu, Sung-Chul Lee