Abstract: In a data processing system having a main store addressed by system addresses and a buffer addressed by logical addresses, where more than one logical address may map to a single system address, a translation buffer is adapted to provide a means for linking translation buffer locations that may map to a given system address to identify all synonym logical addresses. The implementation includes a list header table that generates a pointer to the translation buffer in response to a system address. A search of the translation buffer beginning at the location identified by the list header table and proceeding through each linked location is carried out to identify all synonym logical addresses. The synonym logical addresses are associated by an exclusive ordered list and a means is provided for updating the exclusive list when new entries are made in the translation buffer or old entries are deleted.

Abstract: Disclosed is an apparatus for storing data wherein there are at least two storage units which are addressed by different addressing schemes. The primary storage unit is addressed with a unique addressing scheme while the other storage units are addressed with a scheme wherein more than one of the other addresses may map to a single unique primary address. The apparatus for storing data includes a mechanism for translating all of the unique primary addresses to all of the other addresses which map to that unique primary address.