Patents by Inventor Gyanaranjan Pattanaik

Gyanaranjan Pattanaik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153781
    Abstract: Embodiments of methods are provided for thermal dry etching of a ruthenium (Ru) metal layer. In the disclosed embodiments, a substrate containing a Ru metal layer formed thereon is exposed to a gas pulse sequence, while the substrate is held at a relatively high substrate temperature (e.g., a temperature greater than or equal to about 160° C.), to provide thermal etching of the Ru metal layer. As described further herein, the gas pulse sequence may generally include a plurality of gas pulses, which are supplied to the substrate sequentially with substantially no overlap between gas pulses. The gas pulses supplied to the substrate form: (i) volatile reaction products that are vaporized from the Ru surface, and (ii) non-volatile oxide surface layers that are removed from the Ru surface by the next gas pulse, resulting in atomic layer etching (ALE) of the Ru metal layer.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 9, 2024
    Inventors: Hisashi Higuchi, Kai-Hung Yu, Cory Wajda, Gyanaranjan Pattanaik, Kandabara Tapily, Gerrit Leusink, Robert Clark
  • Patent number: 11621190
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: April 4, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
  • Publication number: 20220301930
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 22, 2022
    Inventors: Kai-Hung Yu, Shihsheng Chang, Ying Trickett, Eric Chih-Fang Liu, Yun Han, Henan Zhang, Cory Wajda, Robert D. Clark, Gerrit J. Leusink, Gyanaranjan Pattanaik, Hiroaki Niimi
  • Patent number: 11171060
    Abstract: A semiconductor device and a method of forming a semiconductor device. The semiconductor device includes a first raised feature in a n-type channel field effect transistor (NFET) region on a substrate, a first doped epitaxial semiconductor material grown on the first raised feature, a first metal contact on the first doped epitaxial semiconductor material, a first metal nitride on the first metal contact, and a first ruthenium (Ru) metal plug on the first metal nitride. The device further includes a second raised feature in a p-type channel field effect transistor (PFET) region on the substrate, a second doped epitaxial semiconductor material grown on the second raised feature, a second metal contact on the second doped epitaxial semiconductor material, a second metal nitride on the second metal contact, and a second ruthenium (Ru) metal plug on the second metal nitride.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 9, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Hiroaki Niimi, Gyanaranjan Pattanaik
  • Publication number: 20210287936
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
  • Patent number: 11024535
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: June 1, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
  • Publication number: 20200279782
    Abstract: A semiconductor device and a method of forming a semiconductor device. The semiconductor device includes a first raised feature in a n-type channel field effect transistor (NFET) region on a substrate, a first doped epitaxial semiconductor material grown on the first raised feature, a first metal contact on the first doped epitaxial semiconductor material, a first metal nitride on the first metal contact, and a first ruthenium (Ru) metal plug on the first metal nitride. The device further includes a second raised feature in a p-type channel field effect transistor (PFET) region on the substrate, a second doped epitaxial semiconductor material grown on the second raised feature, a second metal contact on the second doped epitaxial semiconductor material, a second metal nitride on the second metal contact, and a second ruthenium (Ru) metal plug on the second metal nitride.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 3, 2020
    Inventors: Hiroaki Niimi, Gyanaranjan Pattanaik
  • Publication number: 20200118871
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 16, 2020
    Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink