Abstract: An apparatus for protecting the data in a local register cache during calls and returns that cross subsystem boundaries. The left most bit of a shift register is set to a 1 if a "set boundary bit" instruction is detected. A subsequent PUSH instruction shifts the shift register right one bit. A POPTOS1 instruction in the instruction flow signifies an intra-subsystem return and causes the leftmost bit of the shift register to be checked to see if it is a zero. A protection fault is signalled upon the condition that the leftmost bit is not equal to zero. The shift register is shifted left one bit upon the condition that a POPSTOS 2 instruction is detected. A POPSUB1 instruction detected in the instruction flow signifies an inter-subsystem return and causes the leftmost bit of the shift register to be checked to see if it is a one. A a protection fault is signalled upon the condition that the leftmost bit is not equal to zero.

Abstract: A processor in which instructions and data at logical addresses are mapped onto real memory locations at physical addresses that are translated from the logical addresses by a translation lookaside buffer (TLB) that takes one clock phase to perform this function. The TLB only needs the upper 20 bits of a logical address, which bits correspond to the logical page number, to do the translation to a physical address. The lower 12 bits are not needed until the TLB translation is done. The add of the "base-plus-displacement/offset" usually does not cross a page boundary, that is, the upper 20 bits are the same after the add. A mechanism takes this into account and guesses that the upper 20 bits will not change, and sends them to the TLB. In parallel with the TLB translation, the effective address add of the "base-plus-displacement" is computed.