Abstract: A clock supply device for distributing a source clock signal to memory elements in a synchronous memory system reduces skew and improves accuracy by transmitting a first clock signal from a synchronization section located at a first position to a clock distribution section located at a second position and then feeding back a second clock signal to the synchronization section which includes a phase locked loop or delay locked loop. The synchronization section locks the first signal with the source clock signal, thereby controlling the skew between the first clock signal and the source clock signal. The clock distributing section distributes the first clock signal to memory elements and generates the second clock signal as a feedback signal responsive to the first clock signal.