Abstract: Provided is an immunomodulatory treatment composition for a transplantation disease through combined administration of a microbiome and an immunosuppressant. According to the present disclosure, it was confirmed that in an allogeneic transplantation cell model, combined administration of FK506 and the microbiome suppressed alloresponse and regulated the activity of T cells and B cells. Further, it was confirmed that in an acute graft-versus-host disease animal model, the combined administration reduced the disease activity, increased the probability of survival, and protected the tissue damage. In addition, it was confirmed that the combined administration improved transplantation rejection diseases by reducing the activity of Th1 and Th17 and increasing the activity of Tregs, and thus can be usefully used as an immunomodulator for transplantation rejection.

Abstract: An image device may include a clock generator to generate a first output clock of a first frequency, a link layer to generate a control signal for changing the first frequency and output first parallel data including first frame information, a detector to generate a collision avoidance command to change the first frequency to a second frequency during a vertical blanking time, and a frequency changer to receive the collision avoidance command from the detector and transmit a frequency change command to the link layer. The link layer transmits the control signal to the clock generator based on the frequency change command. The vertical blanking time is a time period from a first time point at which the first parallel data is not output from the link layer to a second time point at which second parallel data is output.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: An image device may include a clock generator to generate a first output clock of a first frequency, a link layer to generate a control signal for changing the first frequency and output first parallel data including first frame information, a detector to generate a collision avoidance command to change the first frequency to a second frequency during a vertical blanking time, and a frequency changer to receive the collision avoidance command from the detector and transmit a frequency change command to the link layer. The link layer transmits the control signal to the clock generator based on the frequency change command. The vertical blanking time is a time period from a first time point at which the first parallel data is not output from the link layer to a second time point at which second parallel data is output.

Abstract: The present disclosure provides an electron generation apparatus includes: a discharge pin module having a support plate and a plurality of discharge pins coupled to the support plate; a discharge plate module disposed to be spaced apart from the plurality of discharge pins; a discharge plate slidably coupled inside the discharge plate module; a support structure having a coupling plate to which the discharge pin module and the discharge plate module are detachably coupled; and a circuit module having a main board located at a side opposite to the discharge pin module with the coupling plate being interposed therebetween and a plurality of distributed processing boards connected to the main board to apply a high-voltage, high-frequency pulse power to the plurality of discharge pins individually.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A system on chip is provided. The system on chip includes a delay control circuit configured to generate delayed clock signals having different delays, based on each of a first rising edge and a first falling edge of an input clock signal, and generate delayed data signals having different delays, based on each of a second rising edge and a second falling edge of an input data signal. The system on chip further includes a de-skew control circuit configured to control the delay control circuit to adjust a delay of each of the first rising edge, the first falling edge, the second rising edge, and the second falling edge.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A system on chip is provided. The system on chip includes a delay control circuit configured to generate delayed clock signals having different delays, based on each of a first rising edge and a first falling edge of an input clock signal, and generate delayed data signals having different delays, based on each of a second rising edge and a second falling edge of an input data signal. The system on chip further includes a de-skew control circuit configured to control the delay control circuit to adjust a delay of each of the first rising edge, the first falling edge, the second rising edge, and the second falling edge.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: An apparatus and method for remotely controlling household appliances connected to a home network. A power line and a network processor is installed in each household appliance, enabling a household appliance user to remotely control the appliances from a place outside of as well as inside a home. Information about all conditions of the household appliances can be displayed on a screen displayable household appliance so that the user can recognize the operations of the appliances even during spare moments. A low-price built-in server is installed in each household appliance to assign the corresponding appliance a unique IP address simply over the Internet to be controlled according to an external user control command. A home server is connected to each of the household appliances such that the corresponding appliance receives a control command, sent in transit by a user from a mobile terminal.