Patents by Inventor Gyeong Hee Lee

Gyeong Hee Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11508771
    Abstract: An image sensor includes a semiconductor substrate having a first surface and a second surface, a pixel element isolation film extending through an interior of the semiconductor substrate and defining a plurality of active pixels in the semiconductor substrate, and a dummy element isolation film extending through the interior of the semiconductor substrate and extending along at least one side of the active pixels in a plan view and defining a plurality of dummy pixels in the semiconductor substrate. The pixel element isolation film may have a first end that is substantially coplanar with the first surface and has a first width in a first direction parallel to the first surface, and the dummy element isolation film has a first end that is substantially coplanar with the first surface and has a second width that is greater than the first width of the pixel element isolation film.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: November 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-han Han, Sun-hyun Kim, Han-seok Kim, Chung-ho Song, Gyeong-hee Lee, Hee-geun Jeong
  • Publication number: 20210265397
    Abstract: An image sensor includes a semiconductor substrate having a first surface and a second surface, a pixel element isolation film extending through an interior of the semiconductor substrate and defining a plurality of active pixels in the semiconductor substrate, and a dummy element isolation film extending through the interior of the semiconductor substrate and extending along at least one side of the active pixels in a plan view and defining a plurality of dummy pixels in the semiconductor substrate. The pixel element isolation film may have a first end that is substantially coplanar with the first surface and has a first width in a first direction parallel to the first surface, and the dummy element isolation film has a first end that is substantially coplanar with the first surface and has a second width that is greater than the first width of the pixel element isolation film.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 26, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-han HAN, Sun-hyun KIM, Han-seok KIM, Chung-ho SONG, Gyeong-hee LEE, Hee-geun JEONG
  • Patent number: 10991742
    Abstract: An image sensor includes a semiconductor substrate having a first surface and a second surface, a pixel element isolation film extending through an interior of the semiconductor substrate and defining a plurality of active pixels in the semiconductor substrate, and a dummy element isolation film extending through the interior of the semiconductor substrate and extending along at least one side of the active pixels in a plan view and defining a plurality of dummy pixels in the semiconductor substrate. The pixel element isolation film may have a first end that is substantially coplanar with the first surface and has a first width in a first direction parallel to the first surface, and the dummy element isolation film has a first end that is substantially coplanar with the first surface and has a second width that is greater than the first width of the pixel element isolation film.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-han Han, Sun-Hyun Kim, Han-seok Kim, Chung-ho Song, Gyeong-hee Lee, Hee-geun Jeong
  • Patent number: 10707232
    Abstract: A method for fabricating a semiconductor device, including forming a lower structure on a substrate. The lower structure includes a first sacrificial layer and a first insulating layer alternately and repeatedly stacked. A first hole is formed in the lower substrate. The first hole exposes an upper surface of the substrate. A sacrificial pattern is formed in the first hole. A porosity of the sacrificial pattern increases toward the substrate. An upper structure is formed on the lower structure and the sacrificial pattern. The upper structure includes a second sacrificial layer and a second insulating layer alternatively and repeatedly stacked. A second hole is formed in the upper structure. The second hole exposes the sacrificial pattern. The sacrificial pattern is removed.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyeong Hee Lee, Jun Yeong Lee
  • Publication number: 20200075643
    Abstract: An image sensor includes a semiconductor substrate having a first surface and a second surface, a pixel element isolation film extending through an interior of the semiconductor substrate and defining a plurality of active pixels in the semiconductor substrate, and a dummy element isolation film extending through the interior of the semiconductor substrate and extending along at least one side of the active pixels in a plan view and defining a plurality of dummy pixels in the semiconductor substrate. The pixel element isolation film may have a first end that is substantially coplanar with the first surface and has a first width in a first direction parallel to the first surface, and the dummy element isolation film has a first end that is substantially coplanar with the first surface and has a second width that is greater than the first width of the pixel element isolation film.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-han HAN, Sun-hyun KIM, Han-seok KIM, Chung-ho SONG, Gyeong-hee LEE, Hee-geun JEONG
  • Publication number: 20190348432
    Abstract: A method for fabricating a semiconductor device, including forming a lower structure on a substrate. The lower structure includes a first sacrificial layer and a first insulating layer alternately and repeatedly stacked. A first hole is formed in the lower substrate. The first hole exposes an upper surface of the substrate. A sacrificial pattern is formed in the first hole. A porosity of the sacrificial pattern increases toward the substrate. An upper structure is formed on the lower structure and the sacrificial pattern. The upper structure includes a second sacrificial layer and a second insulating layer alternatively and repeatedly stacked. A second hole is formed in the upper structure. The second hole exposes the sacrificial pattern. The sacrificial pattern is removed.
    Type: Application
    Filed: December 11, 2018
    Publication date: November 14, 2019
    Inventors: Gyeong Hee Lee, Jun Yeong Lee